FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Specify min tox and venv versions

Browse Source
This commit is contained in:
Alex Forencich 2021-12-27 16:53:30 -08:00
parent 5cf2bcec4d
commit 7f9657009b
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tox.ini
View File

@ -2,6 +2,8 @@
[tox]
envlist = py3
skipsdist = True
minversion = 3.2.0
requires = virtualenv >= 16.1
[gh-actions]
python =