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https://github.com/alexforencich/verilog-ethernet.git
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Move timestamp capture into payload state in XGMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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f37bb1fc8d
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@ -221,10 +221,6 @@ always @* begin
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if (xgmii_start_d1 && cfg_rx_enable) begin
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// start condition
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if (PTP_TS_ENABLE) begin
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m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (PTP_TS_WIDTH != 96 || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
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end
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if (framing_error_reg) begin
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// control or error characters in first data word
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m_axis_tdata_next = {DATA_WIDTH{1'b0}};
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@ -250,6 +246,10 @@ always @* begin
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m_axis_tlast_next = 1'b0;
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m_axis_tuser_next[0] = 1'b0;
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if (PTP_TS_ENABLE) begin
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m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (PTP_TS_WIDTH != 96 || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
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end
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if (framing_error_reg) begin
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// control or error characters in packet
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m_axis_tlast_next = 1'b1;
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