FPGA/verilog-ethernet
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Move header valid assign to top

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This commit is contained in:
Alex Forencich 2014-09-25 16:25:37 -07:00
parent c6236bc647
commit 8191b38e7a
2 changed files with 2 additions and 2 deletions
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2
rtl/ip_eth_rx.v
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@ -199,10 +199,10 @@ reg temp_ip_payload_tuser_reg = 0;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_ip_hdr_valid = output_ip_hdr_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_ip_hdr_valid = output_ip_hdr_valid_reg;
assign output_ip_version = output_ip_version_reg;
assign output_ip_ihl = output_ip_ihl_reg;
assign output_ip_dscp = output_ip_dscp_reg;

2
rtl/ip_eth_rx_64.v
View File

@ -207,10 +207,10 @@ reg shift_eth_payload_extra_cycle;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_ip_hdr_valid = output_ip_hdr_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_ip_hdr_valid = output_ip_hdr_valid_reg;
assign output_ip_version = output_ip_version_reg;
assign output_ip_ihl = output_ip_ihl_reg;
assign output_ip_dscp = output_ip_dscp_reg;