FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

merged changes in axis

Browse Source
This commit is contained in:
Alex Forencich 2021-06-02 17:06:26 -07:00
commit 846183bc8b
34 changed files with 185 additions and 135 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
lib/axis/rtl/arbiter.v
View File

@ -1,6 +1,6 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
@ -32,12 +32,14 @@ THE SOFTWARE.
module arbiter #
(
parameter PORTS = 4,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter TYPE = "PRIORITY",
// block type: "NONE", "REQUEST", "ACKNOWLEDGE"
parameter BLOCK = "NONE",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// blocking arbiter enable
parameter ARB_BLOCK = 0,
// block on acknowledge assert when nonzero, request deassert when 0
parameter ARB_BLOCK_ACK = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 0
)
(
input wire clk,
@ -65,7 +67,7 @@ wire [PORTS-1:0] request_mask;
priority_encoder #(
.WIDTH(PORTS),
.LSB_PRIORITY(LSB_PRIORITY)
.LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
priority_encoder_inst (
.input_unencoded(request),
@ -82,7 +84,7 @@ wire [PORTS-1:0] masked_request_mask;
priority_encoder #(
.WIDTH(PORTS),
.LSB_PRIORITY(LSB_PRIORITY)
.LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
priority_encoder_masked (
.input_unencoded(request & mask_reg),
@ -97,41 +99,41 @@ always @* begin
grant_encoded_next = 0;
mask_next = mask_reg;
if (BLOCK == "REQUEST" && grant_reg & request) begin
if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin
// granted request still asserted; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin
// granted request not yet acknowledged; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (request_valid) begin
if (TYPE == "PRIORITY") begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
end else if (TYPE == "ROUND_ROBIN") begin
if (ARB_TYPE_ROUND_ROBIN) begin
if (masked_request_valid) begin
grant_valid_next = 1;
grant_next = masked_request_mask;
grant_encoded_next = masked_request_index;
if (LSB_PRIORITY == "LOW") begin
mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
end else begin
if (ARB_LSB_HIGH_PRIORITY) begin
mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
end else begin
mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
end
end else begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
if (LSB_PRIORITY == "LOW") begin
mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
end else begin
if (ARB_LSB_HIGH_PRIORITY) begin
mask_next = {PORTS{1'b1}} << (request_index + 1);
end else begin
mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
end
end
end else begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
end
end
end

15
lib/axis/rtl/axis_arb_mux.v
View File

@ -51,10 +51,10 @@ module axis_arb_mux #
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
@ -119,9 +119,10 @@ wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),

12
lib/axis/rtl/axis_arb_mux_wrap.py
View File

@ -86,10 +86,10 @@ module {{name}} #
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
@ -132,8 +132,8 @@ axis_arb_mux #(
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
axis_arb_mux_inst (
.clk(clk),

34
lib/axis/rtl/axis_ram_switch.v
View File

@ -90,10 +90,10 @@ module axis_ram_switch #
// Interface connection control
// M_COUNT concatenated fields of S_COUNT bits
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "ROUND_ROBIN",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH",
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1,
// RAM read data output pipeline stages
parameter RAM_PIPELINE = 2
)
@ -263,9 +263,9 @@ if (S_COUNT > 1) begin
arbiter #(
.PORTS(S_COUNT),
.TYPE("ROUND_ROBIN"),
.BLOCK("NONE"),
.LSB_PRIORITY("HIGH")
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_BLOCK(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
ram_write_arb_inst (
.clk(clk),
@ -299,9 +299,9 @@ if (M_COUNT > 1) begin
arbiter #(
.PORTS(M_COUNT),
.TYPE("ROUND_ROBIN"),
.BLOCK("NONE"),
.LSB_PRIORITY("HIGH")
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_BLOCK(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
ram_read_arb_inst (
.clk(clk),
@ -483,9 +483,10 @@ generate
arbiter #(
.PORTS(M_COUNT),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
cmd_status_arb_inst (
.clk(clk),
@ -802,9 +803,10 @@ generate
arbiter #(
.PORTS(S_COUNT),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
cmd_arb_inst (
.clk(clk),

12
lib/axis/rtl/axis_ram_switch_wrap.py
View File

@ -126,10 +126,10 @@ module {{name}} #
// Interface connection control
parameter M{{'%02d'%p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
{%- endfor %}
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "ROUND_ROBIN",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH",
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1,
// RAM read data output pipeline stages
parameter RAM_PIPELINE = 2
)
@ -204,8 +204,8 @@ axis_ram_switch #(
.M_BASE({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_BASE){% if not loop.last %}, {% endif %}{% endfor %} }),
.M_TOP({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_TOP){% if not loop.last %}, {% endif %}{% endfor %} }),
.M_CONNECT({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT){% if not loop.last %}, {% endif %}{% endfor %} }),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
)
axis_ram_switch_inst (

15
lib/axis/rtl/axis_switch.v
View File

@ -71,10 +71,10 @@ module axis_switch #
// Output interface register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_REG_TYPE = 2,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "ROUND_ROBIN",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
@ -298,9 +298,10 @@ generate
arbiter #(
.PORTS(S_COUNT),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),

12
lib/axis/rtl/axis_switch_wrap.py
View File

@ -107,10 +107,10 @@ module {{name}} #
// Output interface register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_REG_TYPE = 2,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "ROUND_ROBIN",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
@ -169,8 +169,8 @@ axis_switch #(
.M_CONNECT({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT){% if not loop.last %}, {% endif %}{% endfor %} }),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
axis_switch_inst (
.clk(clk),

22
lib/axis/rtl/priority_encoder.v
View File

@ -1,6 +1,6 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
@ -32,8 +32,8 @@ THE SOFTWARE.
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
// LSB priority selection
parameter LSB_HIGH_PRIORITY = 0
)
(
input wire [WIDTH-1:0] input_unencoded,
@ -57,10 +57,12 @@ generate
// process input bits; generate valid bit and encoded bit for each pair
for (n = 0; n < W/2; n = n + 1) begin : loop_in
assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
if (LSB_PRIORITY == "LOW") begin
assign stage_enc[0][n] = input_padded[n*2+1];
end else begin
if (LSB_HIGH_PRIORITY) begin
// bit 0 is highest priority
assign stage_enc[0][n] = !input_padded[n*2+0];
end else begin
// bit 0 is lowest priority
assign stage_enc[0][n] = input_padded[n*2+1];
end
end
@ -68,10 +70,12 @@ generate
for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
if (LSB_PRIORITY == "LOW") begin
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
end else begin
if (LSB_HIGH_PRIORITY) begin
// bit 0 is highest priority
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
end else begin
// bit 0 is lowest priority
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
end
end
end

6
lib/axis/tb/axis_arb_mux/Makefile
View File

@ -47,6 +47,8 @@ export PARAM_DEST_ENABLE ?= 1
export PARAM_DEST_WIDTH ?= 8
export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -60,6 +62,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -77,6 +81,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH)
COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE)
COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH)
COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

5
lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py
View File

@ -284,9 +284,10 @@ tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
@pytest.mark.parametrize("round_robin", [0, 1])
@pytest.mark.parametrize("data_width", [8, 16, 32])
@pytest.mark.parametrize("ports", [1, 4])
def test_axis_arb_mux(request, ports, data_width):
def test_axis_arb_mux(request, ports, data_width, round_robin):
dut = "axis_arb_mux"
wrapper = f"{dut}_wrap_{ports}"
module = os.path.splitext(os.path.basename(__file__))[0]
@ -320,6 +321,8 @@ def test_axis_arb_mux(request, ports, data_width):
parameters['DEST_WIDTH'] = 8
parameters['USER_ENABLE'] = 1
parameters['USER_WIDTH'] = 1
parameters['ARB_TYPE_ROUND_ROBIN'] = round_robin
parameters['ARB_LSB_HIGH_PRIORITY'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

6
lib/axis/tb/axis_ram_switch/Makefile
View File

@ -58,6 +58,8 @@ export PARAM_USER_BAD_FRAME_VALUE ?= 1
export PARAM_USER_BAD_FRAME_MASK ?= 1
export PARAM_DROP_BAD_FRAME ?= 0
export PARAM_DROP_WHEN_FULL ?= 0
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
export PARAM_RAM_PIPELINE ?= 2
ifeq ($(SIM), icarus)
@ -81,6 +83,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME)
COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL)
COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
ifeq ($(WAVES), 1)
@ -108,6 +112,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK)
COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME)
COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL)
COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
ifeq ($(WAVES), 1)

2
lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py
View File

@ -343,6 +343,8 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width):
parameters['USER_BAD_FRAME_MASK'] = 1
parameters['DROP_BAD_FRAME'] = 0
parameters['DROP_WHEN_FULL'] = 0
parameters['ARB_TYPE_ROUND_ROBIN'] = 1
parameters['ARB_LSB_HIGH_PRIORITY'] = 1
parameters['RAM_PIPELINE'] = 2
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

6
lib/axis/tb/axis_switch/Makefile
View File

@ -50,6 +50,8 @@ export PARAM_USER_ENABLE ?= 1
export PARAM_USER_WIDTH ?= 1
export PARAM_S_REG_TYPE ?= 0
export PARAM_M_REG_TYPE ?= 2
export PARAM_ARB_TYPE_ROUND_ROBIN ?= 1
export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -64,6 +66,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).S_REG_TYPE=$(PARAM_S_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).M_REG_TYPE=$(PARAM_M_REG_TYPE)
COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -82,6 +86,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH)
COMPILE_ARGS += -GS_REG_TYPE=$(PARAM_S_REG_TYPE)
COMPILE_ARGS += -GM_REG_TYPE=$(PARAM_M_REG_TYPE)
COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

2
lib/axis/tb/axis_switch/test_axis_switch.py
View File

@ -334,6 +334,8 @@ def test_axis_switch(request, s_count, m_count, data_width):
parameters['USER_WIDTH'] = 1
parameters['S_REG_TYPE'] = 0
parameters['M_REG_TYPE'] = 2
parameters['ARB_TYPE_ROUND_ROBIN'] = 1
parameters['ARB_LSB_HIGH_PRIORITY'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

6
lib/axis/tb/test_arbiter.py
View File

@ -43,8 +43,10 @@ def bench():
# Parameters
PORTS = 32
TYPE = "PRIORITY"
BLOCK = "REQUEST"
ARB_TYPE_ROUND_ROBIN = 0
ARB_BLOCK = 1
ARB_BLOCK_ACK = 0
ARB_LSB_HIGH_PRIORITY = 0
# Inputs
clk = Signal(bool(0))

12
lib/axis/tb/test_arbiter.v
View File

@ -33,8 +33,10 @@ module test_arbiter;
// Parameters
localparam PORTS = 32;
localparam TYPE = "PRIORITY";
localparam BLOCK = "REQUEST";
localparam ARB_TYPE_ROUND_ROBIN = 0;
localparam ARB_BLOCK = 1;
localparam ARB_BLOCK_ACK = 0;
localparam ARB_LSB_HIGH_PRIORITY = 0;
// Inputs
reg clk = 0;
@ -71,8 +73,10 @@ end
arbiter #(
.PORTS(PORTS),
.TYPE(TYPE),
.BLOCK(BLOCK)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(ARB_BLOCK),
.ARB_BLOCK_ACK(ARB_BLOCK_ACK),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),

6
lib/axis/tb/test_arbiter_rr.py
View File

@ -43,8 +43,10 @@ def bench():
# Parameters
PORTS = 32
TYPE = "ROUND_ROBIN"
BLOCK = "REQUEST"
ARB_TYPE_ROUND_ROBIN = 1
ARB_BLOCK = 1
ARB_BLOCK_ACK = 0
ARB_LSB_HIGH_PRIORITY = 0
# Inputs
clk = Signal(bool(0))

12
lib/axis/tb/test_arbiter_rr.v
View File

@ -33,8 +33,10 @@ module test_arbiter_rr;
// Parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";
localparam ARB_TYPE_ROUND_ROBIN = 1;
localparam ARB_BLOCK = 1;
localparam ARB_BLOCK_ACK = 0;
localparam ARB_LSB_HIGH_PRIORITY = 0;
// Inputs
reg clk = 0;
@ -71,8 +73,10 @@ end
arbiter #(
.PORTS(PORTS),
.TYPE(TYPE),
.BLOCK(BLOCK)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(ARB_BLOCK),
.ARB_BLOCK_ACK(ARB_BLOCK_ACK),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),

4
lib/axis/tb/test_axis_arb_mux_4.py
View File

@ -55,8 +55,8 @@ def bench():
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
ARB_TYPE = "PRIORITY"
LSB_PRIORITY = "HIGH"
ARB_TYPE_ROUND_ROBIN = 0
ARB_LSB_HIGH_PRIORITY = 1
# Inputs
clk = Signal(bool(0))

8
lib/axis/tb/test_axis_arb_mux_4.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY";
parameter LSB_PRIORITY = "HIGH";
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
@ -113,8 +113,8 @@ axis_arb_mux #(
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),

4
lib/axis/tb/test_axis_arb_mux_4_64.py
View File

@ -55,8 +55,8 @@ def bench():
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
ARB_TYPE = "PRIORITY"
LSB_PRIORITY = "HIGH"
ARB_TYPE_ROUND_ROBIN = 0
ARB_LSB_HIGH_PRIORITY = 1
# Inputs
clk = Signal(bool(0))

8
lib/axis/tb/test_axis_arb_mux_4_64.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY";
parameter LSB_PRIORITY = "HIGH";
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
@ -113,8 +113,8 @@ axis_arb_mux #(
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),

4
lib/axis/tb/test_axis_ram_switch_1x4_256_64.py
View File

@ -70,8 +70,8 @@ def bench():
M_BASE = [0, 1, 2, 3]
M_TOP = [0, 1, 2, 3]
M_CONNECT = [0b1111]*M_COUNT
ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH"
ARB_TYPE_ROUND_ROBIN = 1
ARB_LSB_HIGH_PRIORITY = 1
RAM_PIPELINE = 2
# Inputs

8
lib/axis/tb/test_axis_ram_switch_1x4_256_64.v
View File

@ -54,8 +54,8 @@ parameter DROP_WHEN_FULL = 0;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
parameter RAM_PIPELINE = 2;
// Inputs
@ -142,8 +142,8 @@ axis_ram_switch #(
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
)
UUT (

4
lib/axis/tb/test_axis_ram_switch_4x1_64_256.py
View File

@ -70,8 +70,8 @@ def bench():
M_BASE = [0, 1, 2, 3]
M_TOP = [0, 1, 2, 3]
M_CONNECT = [0b1111]*M_COUNT
ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH"
ARB_TYPE_ROUND_ROBIN = 1
ARB_LSB_HIGH_PRIORITY = 1
RAM_PIPELINE = 2
# Inputs

8
lib/axis/tb/test_axis_ram_switch_4x1_64_256.v
View File

@ -54,8 +54,8 @@ parameter DROP_WHEN_FULL = 0;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
parameter RAM_PIPELINE = 2;
// Inputs
@ -142,8 +142,8 @@ axis_ram_switch #(
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
)
UUT (

4
lib/axis/tb/test_axis_ram_switch_4x4_64_64.py
View File

@ -68,8 +68,8 @@ def bench():
M_BASE = [0, 1, 2, 3]
M_TOP = [0, 1, 2, 3]
M_CONNECT = [0b1111]*M_COUNT
ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH"
ARB_TYPE_ROUND_ROBIN = 1
ARB_LSB_HIGH_PRIORITY = 1
RAM_PIPELINE = 2
# Inputs

8
lib/axis/tb/test_axis_ram_switch_4x4_64_64.v
View File

@ -54,8 +54,8 @@ parameter DROP_WHEN_FULL = 0;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
parameter RAM_PIPELINE = 2;
// Inputs
@ -142,8 +142,8 @@ axis_ram_switch #(
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
)
UUT (

4
lib/axis/tb/test_axis_switch_4x4.py
View File

@ -61,8 +61,8 @@ def bench():
M_CONNECT = [0b1111]*M_COUNT
S_REG_TYPE = 0
M_REG_TYPE = 2
ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH"
ARB_TYPE_ROUND_ROBIN = 1
ARB_LSB_HIGH_PRIORITY = 1
# Inputs
clk = Signal(bool(0))

8
lib/axis/tb/test_axis_switch_4x4.v
View File

@ -47,8 +47,8 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
@ -121,8 +121,8 @@ axis_switch #(
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),

4
lib/axis/tb/test_axis_switch_4x4_64.py
View File

@ -61,8 +61,8 @@ def bench():
M_CONNECT = [0b1111]*M_COUNT
S_REG_TYPE = 0
M_REG_TYPE = 2
ARB_TYPE = "ROUND_ROBIN"
LSB_PRIORITY = "HIGH"
ARB_TYPE_ROUND_ROBIN = 1
ARB_LSB_HIGH_PRIORITY = 1
# Inputs
clk = Signal(bool(0))

8
lib/axis/tb/test_axis_switch_4x4_64.v
View File

@ -47,8 +47,8 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
@ -121,8 +121,8 @@ axis_switch #(
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),

1
lib/axis/tb/test_priority_encoder.py
View File

@ -42,6 +42,7 @@ def bench():
# Parameters
WIDTH = 32
LSB_HIGH_PRIORITY = 0
# Inputs
clk = Signal(bool(0))

4
lib/axis/tb/test_priority_encoder.v
View File

@ -33,6 +33,7 @@ module test_priority_encoder;
// Parameters
localparam WIDTH = 32;
localparam LSB_HIGH_PRIORITY = 0;
// Inputs
reg clk = 0;
@ -66,7 +67,8 @@ initial begin
end
priority_encoder #(
.WIDTH(WIDTH)
.WIDTH(WIDTH),
.LSB_HIGH_PRIORITY(LSB_HIGH_PRIORITY)
)
UUT (
.input_unencoded(input_unencoded),