FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Add asserts to check for orphaned payloads

Browse Source
This commit is contained in:
Alex Forencich 2015-05-08 21:25:37 -07:00
parent 8aa5ec5118
commit 8b762a6009
2 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tb/ip_ep.py
View File

@ -420,6 +420,10 @@ def IPFrameSink(clk, rst,
frame.payload = ip_payload_fifo.get()
fifo.put(frame)
# ensure all payloads have been matched to headers
if ip_header_fifo.empty():
assert ip_payload_fifo.empty()
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))

4
tb/udp_ep.py
View File

@ -519,6 +519,10 @@ def UDPFrameSink(clk, rst,
frame.payload = udp_payload_fifo.get()
fifo.put(frame)
# ensure all payloads have been matched to headers
if udp_header_fifo.empty():
assert udp_payload_fifo.empty()
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))