FPGA/verilog-ethernet
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Alex Forencich 2016-06-28 18:58:25 -07:00
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README.md
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@ -93,10 +93,6 @@ Ethernet frame transmitter.
Ethernet frame transmitter with 64 bit datapath for 10G Ethernet.
### eth_crc_N module
CRC logic for Ethernet frame check sequence, N input data bits.
### eth_demux_N module
Ethernet frame demuliplexer with 8 bit data width for gigabit Ethernet.
@ -241,6 +237,10 @@ priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_mux_64.py.
### lfsr module
Fully parametrizable combinatorial parallel LFSR/CRC module.
### udp module
UDP block with 8 bit data width for gigabit Ethernet. Manages UDP packet
@ -354,14 +354,6 @@ Can be generated with arbitrary port counts with udp_mux_64.py.
rtl/eth_axis_rx_64.v : Ethernet frame receiver (64 bit)
rtl/eth_axis_tx.v : Ethernet frame transmitter
rtl/eth_axis_tx_64.v : Ethernet frame transmitter (64 bit)
rtl/eth_crc_8.v : Ethernet CRC logic, 8 bits
rtl/eth_crc_16.v : Ethernet CRC logic, 16 bits
rtl/eth_crc_24.v : Ethernet CRC logic, 24 bits
rtl/eth_crc_32.v : Ethernet CRC logic, 32 bits
rtl/eth_crc_40.v : Ethernet CRC logic, 40 bits
rtl/eth_crc_48.v : Ethernet CRC logic, 48 bits
rtl/eth_crc_56.v : Ethernet CRC logic, 56 bits
rtl/eth_crc_64.v : Ethernet CRC logic, 64 bits
rtl/eth_demux.py : Ethernet frame demultiplexer generator
rtl/eth_demux_4.v : 4 port Ethernet frame demultiplexer
rtl/eth_demux_64.py : Ethernet frame demultiplexer generator (64 bit)
@ -401,6 +393,7 @@ Can be generated with arbitrary port counts with udp_mux_64.py.
rtl/ip_mux_4.v : 4 port IP frame multiplexer
rtl/ip_mux_64.py : IP frame multiplexer generator (64 bit)
rtl/ip_mux_64_4.v : 4 port IP frame multiplexer (64 bit)
rtl/lfsr.v : Generic LFSR/CRC module
rtl/udp.v : UDP block
rtl/udp_64.v : UDP block (64 bit)
rtl/udp_arb_mux.py : UDP frame arbitrated multiplexer generator