FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Initial commit of basic statistics collection module

Browse Source
This commit is contained in:
Alex Forencich 2014-10-21 13:20:37 -07:00
parent 8bce338bc0
commit 8e9b38cde0
3 changed files with 1185 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

299
rtl/axis_stat_counter.v Normal file
View File

@ -0,0 +1,299 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream statistics counter
*/
module axis_stat_counter #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI monitor
*/
input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
input wire monitor_axis_tvalid,
input wire monitor_axis_tready,
input wire monitor_axis_tlast,
/*
* AXI status data output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [15:0] tag,
input wire trigger
);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_OUTPUT_DATA = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [31:0] tick_count_reg = 0, tick_count_next;
reg [31:0] byte_count_reg = 0, byte_count_next;
reg [31:0] frame_count_reg = 0, frame_count_next;
reg frame_reg = 0, frame_next;
reg store_output;
reg [5:0] frame_ptr_reg = 0, frame_ptr_next;
reg [31:0] tick_count_output_reg = 0;
reg [31:0] byte_count_output_reg = 0;
reg [31:0] frame_count_output_reg = 0;
// internal datapath
reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early = output_axis_tready;
function [3:0] keep2count;
input [7:0] k;
case (k)
8'b00000000: keep2count = 0;
8'b00000001: keep2count = 1;
8'b00000011: keep2count = 2;
8'b00000111: keep2count = 3;
8'b00001111: keep2count = 4;
8'b00011111: keep2count = 5;
8'b00111111: keep2count = 6;
8'b01111111: keep2count = 7;
8'b11111111: keep2count = 8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
state_next = 2'bz;
tick_count_next = tick_count_reg;
byte_count_next = byte_count_reg;
frame_count_next = frame_count_reg;
frame_next = frame_reg;
output_axis_tdata_int = 0;
output_axis_tvalid_int = 0;
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
store_output = 0;
frame_ptr_next = frame_ptr_reg;
// data readout
case (state_reg)
STATE_IDLE: begin
if (trigger) begin
store_output = 1;
tick_count_next = 0;
byte_count_next = 0;
frame_count_next = 0;
frame_ptr_next = 0;
if (output_axis_tready_int) begin
frame_ptr_next = 1;
output_axis_tdata_int = tag[15:8];
output_axis_tvalid_int = 1;
end
state_next = STATE_OUTPUT_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_OUTPUT_DATA: begin
if (output_axis_tready_int) begin
state_next = STATE_OUTPUT_DATA;
frame_ptr_next = frame_ptr_reg + 1;
output_axis_tvalid_int = 1;
case (frame_ptr_reg)
5'd00: output_axis_tdata_int = tag[15:8];
5'd01: output_axis_tdata_int = tag[7:0];
5'd02: output_axis_tdata_int = tick_count_output_reg[31:24];
5'd03: output_axis_tdata_int = tick_count_output_reg[23:16];
5'd04: output_axis_tdata_int = tick_count_output_reg[15: 8];
5'd05: output_axis_tdata_int = tick_count_output_reg[ 7: 0];
5'd06: output_axis_tdata_int = byte_count_output_reg[31:24];
5'd07: output_axis_tdata_int = byte_count_output_reg[23:16];
5'd08: output_axis_tdata_int = byte_count_output_reg[15: 8];
5'd09: output_axis_tdata_int = byte_count_output_reg[ 7: 0];
5'd10: output_axis_tdata_int = frame_count_output_reg[31:24];
5'd11: output_axis_tdata_int = frame_count_output_reg[23:16];
5'd12: output_axis_tdata_int = frame_count_output_reg[15: 8];
5'd13: begin
output_axis_tdata_int = frame_count_output_reg[ 7: 0];
output_axis_tlast_int = 1;
state_next = STATE_IDLE;
end
endcase
end else begin
state_next = STATE_OUTPUT_DATA;
end
end
endcase
// stats collection
// increment tick count by number of words that can be transferred per cycle
tick_count_next = tick_count_next + KEEP_WIDTH;
if (monitor_axis_tready & monitor_axis_tvalid) begin
// valid transfer cycle
// increment byte count by number of words transferred
byte_count_next = byte_count_next + keep2count(monitor_axis_tkeep);
// count frames
if (monitor_axis_tlast) begin
// end of frame
frame_next = 0;
end else if (~frame_reg) begin
// first word after end of frame
frame_count_next = frame_count_next + 1;
frame_next = 1;
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
tick_count_reg <= 0;
byte_count_reg <= 0;
frame_count_reg <= 0;
frame_reg <= 0;
frame_ptr_reg <= 0;
tick_count_output_reg <= 0;
byte_count_output_reg <= 0;
frame_count_output_reg <= 0;
end else begin
state_reg <= state_next;
tick_count_reg <= tick_count_next;
byte_count_reg <= byte_count_next;
frame_count_reg <= frame_count_next;
frame_reg <= frame_next;
frame_ptr_reg <= frame_ptr_next;
if (store_output) begin
tick_count_output_reg <= tick_count_reg;
byte_count_output_reg <= byte_count_reg;
frame_count_output_reg <= frame_count_reg;
end
end
end
// output datapath logic
reg [7:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [7:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
// also enable ready input next cycle if output is currently not valid and will not become valid next cycle
output_axis_tready_int <= output_axis_tready | (~output_axis_tvalid_reg & ~output_axis_tvalid_int);
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
end
end
endmodule

788
tb/test_axis_stat_counter.py Executable file
View File

@ -0,0 +1,788 @@
#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import struct
import axis_ep
module = 'axis_stat_counter'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_stat_counter(clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
tag,
trigger):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
monitor_axis_tdata=monitor_axis_tdata,
monitor_axis_tkeep=monitor_axis_tkeep,
monitor_axis_tvalid=monitor_axis_tvalid,
monitor_axis_tready=monitor_axis_tready,
monitor_axis_tlast=monitor_axis_tlast,
monitor_axis_tuser=monitor_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
tag=tag,
trigger=trigger)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
monitor_axis_tdata = Signal(intbv(0)[64:])
monitor_axis_tkeep = Signal(intbv(0)[8:])
monitor_axis_tvalid = Signal(bool(0))
monitor_axis_tready = Signal(bool(0))
monitor_axis_tlast = Signal(bool(0))
monitor_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
tag = Signal(intbv(16)[16:])
trigger = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
monitor_sink_queue = Queue()
monitor_sink_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
monitor_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
fifo=monitor_sink_queue,
pause=monitor_sink_pause,
name='monitor_sink')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_axis_stat_counter(clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
tag,
trigger)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
tag.next = 1
yield clk.posedge
print("test 1: test tick timer")
current_test.next = 1
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
for i in range(100-1):
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[1] == 100*8
yield delay(100)
yield clk.posedge
print("test 2: pause sink")
current_test.next = 2
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
for i in range(100-1):
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
while trigger or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[1] == 100*8
yield delay(100)
yield clk.posedge
print("test 3: test packet")
current_test.next = 3
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 4: longer packet")
current_test.next = 4
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 5: test packet with pauses")
current_test.next = 5
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
monitor_sink_pause.next = True
yield delay(32)
yield clk.posedge
monitor_sink_pause.next = False
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 6: back-to-back packets")
current_test.next = 6
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source")
current_test.next = 7
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink")
current_test.next = 8
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 9: various length packets")
current_test.next = 9
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in range(len(lens)):
test_frame.append(axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == sum(len(f.data) for f in test_frame)
assert rx_frame_values[3] == len(test_frame)
yield delay(100)
yield clk.posedge
print("test 10: various length packets with intermediate trigger")
current_test.next = 10
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in range(len(lens)):
test_frame.append(axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
yield clk.posedge
yield delay(200)
yield clk.posedge
trigger_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame2 = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", rx_frame.data)
cycles = (stop_time - start_time) / 8
cycles1 = (trigger_time - start_time) / 8
print(rx_frame_values)
rx_frame2_values = struct.unpack(">HLLL", rx_frame2.data)
cycles2 = (stop_time - trigger_time) / 8
print(rx_frame2_values)
assert rx_frame_values[0] == 1
assert rx_frame2_values[0] == 1
assert rx_frame_values[1] == cycles1*8
assert rx_frame2_values[1] == cycles2*8
assert rx_frame_values[1] + rx_frame2_values[1] == cycles*8
assert rx_frame_values[2] + rx_frame2_values[2] == sum(len(f.data) for f in test_frame)
assert rx_frame_values[3] + rx_frame2_values[3] == len(test_frame)
yield delay(100)
raise StopSimulation
return dut, source, monitor_sink, sink, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

98
tb/test_axis_stat_counter.v Normal file
View File

@ -0,0 +1,98 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_stat_counter;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] monitor_axis_tdata = 8'd0;
reg [7:0] monitor_axis_tkeep = 8'd0;
reg monitor_axis_tvalid = 1'b0;
reg monitor_axis_tready = 1'b0;
reg monitor_axis_tlast = 1'b0;
reg monitor_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [15:0] tag = 0;
reg trigger = 0;
// Outputs
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tready,
tag,
trigger);
$to_myhdl(output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_stat_counter.lxt");
$dumpvars(0, test_axis_stat_counter);
end
axis_stat_counter #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// axi monitor input
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// configuration
.tag(tag),
.trigger(trigger)
);
endmodule