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https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Properly synchronize bad FCS status output
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@ -227,7 +227,7 @@ always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 2'd0;
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end else begin
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
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end
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end
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@ -166,7 +166,7 @@ always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 2'd0;
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end else begin
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
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end
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end
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@ -178,7 +178,7 @@ always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 2'd0;
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end else begin
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
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end
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end
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@ -178,7 +178,7 @@ always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 2'd0;
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end else begin
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
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end
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end
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@ -171,7 +171,7 @@ always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 2'd0;
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end else begin
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
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end
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end
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@ -243,7 +243,7 @@ always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= 5'd0;
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end else begin
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_high_ber_int, rx_block_lock_int, rx_bad_block_int, rx_error_bad_frame_int, rx_error_bad_frame_int};
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rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_high_ber_int, rx_block_lock_int, rx_bad_block_int, rx_error_bad_fcs_int, rx_error_bad_frame_int};
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end
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end
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