FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity

Internal synchronous reset on async FIFOs

Browse Source
This commit is contained in:
Alex Forencich 2015-10-08 13:03:42 -07:00
parent 30a35c3d73
commit 90ac361df5
4 changed files with 68 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
rtl/axis_async_fifo.v
View File

@ -73,8 +73,10 @@ reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1; reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1; reg input_rst_sync2 = 1;
reg input_rst_sync3 = 1;
reg output_rst_sync1 = 1; reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1; reg output_rst_sync2 = 1;
reg output_rst_sync3 = 1;
reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}}; reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
@ -106,9 +108,11 @@ always @(posedge input_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
input_rst_sync1 <= 1; input_rst_sync1 <= 1;
input_rst_sync2 <= 1; input_rst_sync2 <= 1;
input_rst_sync3 <= 1;
end else begin end else begin
input_rst_sync1 <= 0; input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1; input_rst_sync2 <= input_rst_sync1 | output_rst_sync1;
input_rst_sync3 <= input_rst_sync2;
end end
end end
@ -116,15 +120,17 @@ always @(posedge output_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
output_rst_sync1 <= 1; output_rst_sync1 <= 1;
output_rst_sync2 <= 1; output_rst_sync2 <= 1;
output_rst_sync3 <= 1;
end else begin end else begin
output_rst_sync1 <= 0; output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1; output_rst_sync2 <= output_rst_sync1;
output_rst_sync3 <= output_rst_sync2;
end end
end end
// write // write
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
wr_ptr <= 0; wr_ptr <= 0;
wr_ptr_gray <= 0; wr_ptr_gray <= 0;
end else if (write) begin end else if (write) begin
@ -136,8 +142,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
rd_ptr_gray_sync1 <= 0; rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0; rd_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -147,8 +153,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// read // read
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
rd_ptr <= 0; rd_ptr <= 0;
rd_ptr_gray <= 0; rd_ptr_gray <= 0;
end else if (read) begin end else if (read) begin
@ -160,8 +166,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
wr_ptr_gray_sync1 <= 0; wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0; wr_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -171,8 +177,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// source ready output // source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
output_axis_tvalid_reg <= 1'b0; output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty; output_axis_tvalid_reg <= ~empty;

28
rtl/axis_async_fifo_64.v
View File

@ -76,8 +76,10 @@ reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1; reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1; reg input_rst_sync2 = 1;
reg input_rst_sync3 = 1;
reg output_rst_sync1 = 1; reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1; reg output_rst_sync2 = 1;
reg output_rst_sync3 = 1;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}}; reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
@ -109,9 +111,11 @@ always @(posedge input_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
input_rst_sync1 <= 1; input_rst_sync1 <= 1;
input_rst_sync2 <= 1; input_rst_sync2 <= 1;
input_rst_sync3 <= 1;
end else begin end else begin
input_rst_sync1 <= 0; input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1; input_rst_sync2 <= input_rst_sync1 | output_rst_sync1;
input_rst_sync3 <= input_rst_sync2;
end end
end end
@ -119,15 +123,17 @@ always @(posedge output_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
output_rst_sync1 <= 1; output_rst_sync1 <= 1;
output_rst_sync2 <= 1; output_rst_sync2 <= 1;
output_rst_sync3 <= 1;
end else begin end else begin
output_rst_sync1 <= 0; output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1; output_rst_sync2 <= output_rst_sync1;
output_rst_sync3 <= output_rst_sync2;
end end
end end
// write // write
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
wr_ptr <= 0; wr_ptr <= 0;
wr_ptr_gray <= 0; wr_ptr_gray <= 0;
end else if (write) begin end else if (write) begin
@ -139,8 +145,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
rd_ptr_gray_sync1 <= 0; rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0; rd_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -150,8 +156,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// read // read
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
rd_ptr <= 0; rd_ptr <= 0;
rd_ptr_gray <= 0; rd_ptr_gray <= 0;
end else if (read) begin end else if (read) begin
@ -163,8 +169,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
wr_ptr_gray_sync1 <= 0; wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0; wr_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -174,8 +180,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// source ready output // source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
output_axis_tvalid_reg <= 1'b0; output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty; output_axis_tvalid_reg <= ~empty;

28
rtl/axis_async_frame_fifo.v
View File

@ -81,8 +81,10 @@ reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1; reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1; reg input_rst_sync2 = 1;
reg input_rst_sync3 = 1;
reg output_rst_sync1 = 1; reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1; reg output_rst_sync2 = 1;
reg output_rst_sync3 = 1;
reg drop_frame = 1'b0; reg drop_frame = 1'b0;
reg overflow_reg = 1'b0; reg overflow_reg = 1'b0;
@ -126,9 +128,11 @@ always @(posedge input_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
input_rst_sync1 <= 1; input_rst_sync1 <= 1;
input_rst_sync2 <= 1; input_rst_sync2 <= 1;
input_rst_sync3 <= 1;
end else begin end else begin
input_rst_sync1 <= 0; input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1; input_rst_sync2 <= input_rst_sync1 | output_rst_sync1;
input_rst_sync3 <= input_rst_sync2;
end end
end end
@ -136,15 +140,17 @@ always @(posedge output_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
output_rst_sync1 <= 1; output_rst_sync1 <= 1;
output_rst_sync2 <= 1; output_rst_sync2 <= 1;
output_rst_sync3 <= 1;
end else begin end else begin
output_rst_sync1 <= 0; output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1; output_rst_sync2 <= output_rst_sync1;
output_rst_sync3 <= output_rst_sync2;
end end
end end
// write // write
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
wr_ptr <= 0; wr_ptr <= 0;
wr_ptr_cur <= 0; wr_ptr_cur <= 0;
wr_ptr_gray <= 0; wr_ptr_gray <= 0;
@ -189,8 +195,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
rd_ptr_gray_sync1 <= 0; rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0; rd_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -200,8 +206,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// read // read
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
rd_ptr <= 0; rd_ptr <= 0;
rd_ptr_gray <= 0; rd_ptr_gray <= 0;
end else if (read) begin end else if (read) begin
@ -213,8 +219,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
wr_ptr_gray_sync1 <= 0; wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0; wr_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -224,8 +230,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// source ready output // source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
output_axis_tvalid_reg <= 1'b0; output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty; output_axis_tvalid_reg <= ~empty;

28
rtl/axis_async_frame_fifo_64.v
View File

@ -84,8 +84,10 @@ reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1; reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1; reg input_rst_sync2 = 1;
reg input_rst_sync3 = 1;
reg output_rst_sync1 = 1; reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1; reg output_rst_sync2 = 1;
reg output_rst_sync3 = 1;
reg drop_frame = 1'b0; reg drop_frame = 1'b0;
reg overflow_reg = 1'b0; reg overflow_reg = 1'b0;
@ -129,9 +131,11 @@ always @(posedge input_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
input_rst_sync1 <= 1; input_rst_sync1 <= 1;
input_rst_sync2 <= 1; input_rst_sync2 <= 1;
input_rst_sync3 <= 1;
end else begin end else begin
input_rst_sync1 <= 0; input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1; input_rst_sync2 <= input_rst_sync1 | output_rst_sync1;
input_rst_sync3 <= input_rst_sync2;
end end
end end
@ -139,15 +143,17 @@ always @(posedge output_clk or posedge async_rst) begin
if (async_rst) begin if (async_rst) begin
output_rst_sync1 <= 1; output_rst_sync1 <= 1;
output_rst_sync2 <= 1; output_rst_sync2 <= 1;
output_rst_sync3 <= 1;
end else begin end else begin
output_rst_sync1 <= 0; output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1; output_rst_sync2 <= output_rst_sync1;
output_rst_sync3 <= output_rst_sync2;
end end
end end
// write // write
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
wr_ptr <= 0; wr_ptr <= 0;
wr_ptr_cur <= 0; wr_ptr_cur <= 0;
wr_ptr_gray <= 0; wr_ptr_gray <= 0;
@ -192,8 +198,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin always @(posedge input_clk) begin
if (input_rst_sync2) begin if (input_rst_sync3) begin
rd_ptr_gray_sync1 <= 0; rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0; rd_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -203,8 +209,8 @@ always @(posedge input_clk or posedge input_rst_sync2) begin
end end
// read // read
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
rd_ptr <= 0; rd_ptr <= 0;
rd_ptr_gray <= 0; rd_ptr_gray <= 0;
end else if (read) begin end else if (read) begin
@ -216,8 +222,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// pointer synchronization // pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
wr_ptr_gray_sync1 <= 0; wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0; wr_ptr_gray_sync2 <= 0;
end else begin end else begin
@ -227,8 +233,8 @@ always @(posedge output_clk or posedge output_rst_sync2) begin
end end
// source ready output // source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin always @(posedge output_clk) begin
if (output_rst_sync2) begin if (output_rst_sync3) begin
output_axis_tvalid_reg <= 1'b0; output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty; output_axis_tvalid_reg <= ~empty;