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https://github.com/alexforencich/verilog-ethernet.git
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Cleanup RGMII PHY IF, fix TX error indication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@ -109,57 +109,49 @@ assign mac_gmii_rx_er = rgmii_rx_ctl_1 ^ rgmii_rx_ctl_2;
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reg rgmii_tx_clk_1 = 1'b1;
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reg rgmii_tx_clk_2 = 1'b0;
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reg rgmii_tx_clk_rise = 1'b1;
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reg rgmii_tx_clk_fall = 1'b1;
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reg rgmii_tx_clk_en = 1'b1;
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reg [5:0] count_reg = 6'd0, count_next;
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always @(posedge clk) begin
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rgmii_tx_clk_1 <= rgmii_tx_clk_2;
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if (speed == 2'b00) begin
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// 10M
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count_reg <= count_reg + 1;
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rgmii_tx_clk_en <= 1'b0;
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if (count_reg == 24) begin
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rgmii_tx_clk_1 <= 1'b1;
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rgmii_tx_clk_2 <= 1'b1;
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end else if (count_reg >= 49) begin
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rgmii_tx_clk_2 <= 1'b0;
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rgmii_tx_clk_en <= 1'b1;
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count_reg <= 0;
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end
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end else if (speed == 2'b01) begin
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// 100M
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count_reg <= count_reg + 1;
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rgmii_tx_clk_en <= 1'b0;
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if (count_reg == 2) begin
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rgmii_tx_clk_1 <= 1'b1;
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rgmii_tx_clk_2 <= 1'b1;
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end else if (count_reg >= 4) begin
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rgmii_tx_clk_2 <= 1'b0;
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rgmii_tx_clk_en <= 1'b1;
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count_reg <= 0;
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end
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end else begin
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// 1000M
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rgmii_tx_clk_1 <= 1'b1;
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rgmii_tx_clk_2 <= 1'b0;
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rgmii_tx_clk_en <= 1'b1;
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end
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if (rst) begin
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rgmii_tx_clk_1 <= 1'b1;
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rgmii_tx_clk_2 <= 1'b0;
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rgmii_tx_clk_rise <= 1'b1;
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rgmii_tx_clk_fall <= 1'b1;
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rgmii_tx_clk_en <= 1'b1;
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count_reg <= 0;
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end else begin
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rgmii_tx_clk_1 <= rgmii_tx_clk_2;
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if (speed == 2'b00) begin
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// 10M
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count_reg <= count_reg + 1;
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rgmii_tx_clk_rise <= 1'b0;
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rgmii_tx_clk_fall <= 1'b0;
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if (count_reg == 24) begin
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rgmii_tx_clk_1 <= 1'b1;
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rgmii_tx_clk_2 <= 1'b1;
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rgmii_tx_clk_rise <= 1'b1;
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end else if (count_reg >= 49) begin
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rgmii_tx_clk_1 <= 1'b0;
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rgmii_tx_clk_2 <= 1'b0;
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rgmii_tx_clk_fall <= 1'b1;
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count_reg <= 0;
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end
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end else if (speed == 2'b01) begin
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// 100M
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count_reg <= count_reg + 1;
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rgmii_tx_clk_rise <= 1'b0;
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rgmii_tx_clk_fall <= 1'b0;
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if (count_reg == 2) begin
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rgmii_tx_clk_1 <= 1'b1;
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rgmii_tx_clk_2 <= 1'b1;
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rgmii_tx_clk_rise <= 1'b1;
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end else if (count_reg >= 4) begin
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rgmii_tx_clk_2 <= 1'b0;
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rgmii_tx_clk_fall <= 1'b1;
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count_reg <= 0;
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end
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end else begin
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// 1000M
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rgmii_tx_clk_1 <= 1'b1;
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rgmii_tx_clk_2 <= 1'b0;
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rgmii_tx_clk_rise <= 1'b1;
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rgmii_tx_clk_fall <= 1'b1;
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end
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end
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end
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@ -175,26 +167,26 @@ always @* begin
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// 10M
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rgmii_txd_1 = mac_gmii_txd[3:0];
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rgmii_txd_2 = mac_gmii_txd[3:0];
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if (rgmii_tx_clk_2) begin
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rgmii_tx_ctl_1 = mac_gmii_tx_en;
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rgmii_tx_ctl_2 = mac_gmii_tx_en;
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end else begin
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if (rgmii_tx_clk_1) begin
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rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
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rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
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end else begin
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rgmii_tx_ctl_1 = mac_gmii_tx_en;
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rgmii_tx_ctl_2 = mac_gmii_tx_en;
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end
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gmii_clk_en = rgmii_tx_clk_fall;
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gmii_clk_en = rgmii_tx_clk_en;
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end else if (speed == 2'b01) begin
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// 100M
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rgmii_txd_1 = mac_gmii_txd[3:0];
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rgmii_txd_2 = mac_gmii_txd[3:0];
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if (rgmii_tx_clk_2) begin
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rgmii_tx_ctl_1 = mac_gmii_tx_en;
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rgmii_tx_ctl_2 = mac_gmii_tx_en;
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end else begin
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if (rgmii_tx_clk_1) begin
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rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
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rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
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end else begin
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rgmii_tx_ctl_1 = mac_gmii_tx_en;
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rgmii_tx_ctl_2 = mac_gmii_tx_en;
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end
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gmii_clk_en = rgmii_tx_clk_fall;
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gmii_clk_en = rgmii_tx_clk_en;
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end else begin
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// 1000M
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rgmii_txd_1 = mac_gmii_txd[3:0];
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