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Fix DIC implementation in testbench

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This commit is contained in:
Alex Forencich 2019-01-22 14:23:29 -08:00
parent 9ae60dcd9a
commit 92df3778ea
2 changed files with 4 additions and 4 deletions
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4
tb/baser_serdes_ep.py
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@ -144,7 +144,7 @@ class BaseRSerdesSource(object):
data = 0x000000000000001e
header = 0b01
if (ifg_cnt > bw-1 and self.enable_dic) or ifg_cnt > 0:
if ifg_cnt > bw-1 or (not self.enable_dic and ifg_cnt > 0):
ifg_cnt = max(ifg_cnt - bw, 0)
elif ccl:
header, data = ccl.pop(0)
@ -172,7 +172,7 @@ class BaseRSerdesSource(object):
dl = [XGMII_IDLE]*4+dl
cl = [1]*4+cl
deficit_idle_cnt = ifg_cnt
deficit_idle_cnt = max(ifg_cnt, 0)
ifg_cnt = 0
# pad length to multiple of 8 by adding idles

4
tb/xgmii_ep.py
View File

@ -174,7 +174,7 @@ class XGMIISource(object):
ifg_cnt = 0
deficit_idle_cnt = 0
elif enable:
if (ifg_cnt > bw-1 and self.enable_dic) or ifg_cnt > 0:
if ifg_cnt > bw-1 or (not self.enable_dic and ifg_cnt > 0):
ifg_cnt = max(ifg_cnt - bw, 0)
txd.next = 0x0707070707070707 if bw == 8 else 0x07070707
txc.next = 0xff if bw == 8 else 0xf
@ -212,7 +212,7 @@ class XGMIISource(object):
dl = [XGMII_IDLE]*4+dl
cl = [1]*4+cl
deficit_idle_cnt = ifg_cnt
deficit_idle_cnt = max(ifg_cnt, 0)
ifg_cnt = 0
d = 0