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MAC RX timing optimizations

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This commit is contained in:
Alex Forencich 2019-06-16 00:36:50 -07:00
parent 27999924a0
commit 938479c246
2 changed files with 8 additions and 6 deletions
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7
rtl/axis_xgmii_rx_32.v
View File

@ -286,7 +286,7 @@ always @* begin
last_cycle_tkeep_next = last_cycle_tkeep_reg;
m_axis_tdata_next = {DATA_WIDTH{1'b0}};
m_axis_tkeep_next = {KEEP_WIDTH{1'b0}};
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b0;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
@ -334,11 +334,13 @@ always @* begin
update_crc = 1'b1;
m_axis_tdata_next = xgmii_rxd_d2;
m_axis_tkeep_next = ~xgmii_rxc_d2;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
last_cycle_tkeep_next = tkeep_mask;
if (control_masked) begin
// control or error characters in packet
m_axis_tlast_next = 1'b1;
@ -362,7 +364,6 @@ always @* begin
state_next = STATE_IDLE;
end else begin
// need extra cycle
last_cycle_tkeep_next = tkeep_mask;
state_next = STATE_LAST;
end
end else begin

7
rtl/axis_xgmii_rx_64.v
View File

@ -326,7 +326,7 @@ always @* begin
last_cycle_tkeep_next = last_cycle_tkeep_reg;
m_axis_tdata_next = {DATA_WIDTH{1'b0}};
m_axis_tkeep_next = {KEEP_WIDTH{1'b0}};
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b0;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
@ -364,11 +364,13 @@ always @* begin
update_crc = 1'b1;
m_axis_tdata_next = xgmii_rxd_d1;
m_axis_tkeep_next = ~xgmii_rxc_d1;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
last_cycle_tkeep_next = {4'b0000, tkeep_mask[7:4]};
if (control_masked) begin
// control or error characters in packet
m_axis_tlast_next = 1'b1;
@ -396,7 +398,6 @@ always @* begin
state_next = STATE_IDLE;
end else begin
// need extra cycle
last_cycle_tkeep_next = {4'b0000, tkeep_mask[7:4]};
state_next = STATE_LAST;
end
end else begin