FPGA/verilog-ethernet
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Minor fixes

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This commit is contained in:
Alex Forencich 2019-04-03 20:57:10 -07:00
parent 1bec485766
commit 978fdce95c
1 changed files with 2 additions and 2 deletions
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4
example/Arty/fpga/rtl/fpga.v
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@ -192,7 +192,7 @@ wire [3:0] sw_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(25000)
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
@ -245,7 +245,7 @@ core_inst (
.led6(led6),
.led7(led7),
/*
* Ethernet: 1000BASE-T RGMII
* Ethernet: 100BASE-T MII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),