mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Update readme
This commit is contained in:
parent
cee82cb695
commit
9df253aa59
@ -50,6 +50,7 @@ following boards:
|
||||
* Xilinx ML605 (Xilinx Virtex 6 XC6VLX240T)
|
||||
* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
|
||||
* Digilent Nexys Video (Xilinx Artix 7 XC7A200T)
|
||||
* Intel Stratix 10 DX dev kit (Intel Stratix 10 DX 1SD280PT2F55E1VG)
|
||||
* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 1SM21CHU1F53E1VG)
|
||||
* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
|
||||
* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)
|
||||
|
Loading…
x
Reference in New Issue
Block a user