From 592ae7e6a2321b5ce0580a7a51058bb7017d53f6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 25 Jul 2019 00:40:13 -0700 Subject: [PATCH 1/5] Change default switch addressing to use MSBs of tdest --- rtl/axis_switch.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/axis_switch.v b/rtl/axis_switch.v index c677ec62..ee2810df 100644 --- a/rtl/axis_switch.v +++ b/rtl/axis_switch.v @@ -55,7 +55,7 @@ module axis_switch # // Output interface routing base tdest selection // Concatenate M_COUNT DEST_WIDTH sized constants // Port selected if M_BASE <= tdest <= M_TOP - // set to zero for default routing with tdest as port index + // set to zero for default routing with tdest MSBs as port index parameter M_BASE = 0, // Output interface routing top tdest selection // Concatenate M_COUNT DEST_WIDTH sized constants @@ -188,8 +188,8 @@ generate drop_next = 1'b1; for (k = 0; k < M_COUNT; k = k + 1) begin if (M_BASE == 0) begin - // M_BASE is zero, route with tdest as port index - if (int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin + // M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index + if (int_s_axis_tdest[m*DEST_WIDTH+(DEST_WIDTH-CL_M_COUNT) +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin select_next = k; select_valid_next = 1'b1; drop_next = 1'b0; From 0a85a4a2aaba80cad7ca69c01d9d30639e9c1c8e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 25 Jul 2019 00:43:42 -0700 Subject: [PATCH 2/5] Fix assert --- rtl/axis_switch.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/axis_switch.v b/rtl/axis_switch.v index ee2810df..5352fe22 100644 --- a/rtl/axis_switch.v +++ b/rtl/axis_switch.v @@ -112,7 +112,7 @@ integer i, j; // check configuration initial begin - if (2**DEST_WIDTH < CL_M_COUNT) begin + if (DEST_WIDTH < CL_M_COUNT) begin $error("Error: DEST_WIDTH too small for port count"); $finish; end From ce00df8de150072ed95cef8fb2b6061beb87bfc8 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 25 Jul 2019 16:30:10 -0700 Subject: [PATCH 3/5] Include instance names in error messages --- rtl/axis_adapter.v | 6 +++--- rtl/axis_async_fifo.v | 8 ++++---- rtl/axis_async_fifo_adapter.v | 6 +++--- rtl/axis_fifo.v | 8 ++++---- rtl/axis_fifo_adapter.v | 6 +++--- rtl/axis_frame_length_adjust.v | 2 +- rtl/axis_switch.v | 8 ++++---- 7 files changed, 22 insertions(+), 22 deletions(-) diff --git a/rtl/axis_adapter.v b/rtl/axis_adapter.v index 065ab9f9..68b31a50 100644 --- a/rtl/axis_adapter.v +++ b/rtl/axis_adapter.v @@ -109,17 +109,17 @@ parameter SEGMENT_KEEP_WIDTH = KEEP_WIDTH / SEGMENT_COUNT; // bus width assertions initial begin if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin - $error("Error: input data width not evenly divisble"); + $error("Error: input data width not evenly divisble (instance %m)"); $finish; end if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin - $error("Error: output data width not evenly divisble"); + $error("Error: output data width not evenly divisble (instance %m)"); $finish; end if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin - $error("Error: word size mismatch"); + $error("Error: word size mismatch (instance %m)"); $finish; end end diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v index a3568b78..416cc09c 100644 --- a/rtl/axis_async_fifo.v +++ b/rtl/axis_async_fifo.v @@ -120,22 +120,22 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH // check configuration initial begin if (FRAME_FIFO && !LAST_ENABLE) begin - $error("Error: FRAME_FIFO set requires LAST_ENABLE set"); + $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); $finish; end if (DROP_BAD_FRAME && !FRAME_FIFO) begin - $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set"); + $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)"); $finish; end if (DROP_WHEN_FULL && !FRAME_FIFO) begin - $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set"); + $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)"); $finish; end if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin - $error("Error: Invalid USER_BAD_FRAME_MASK value"); + $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); $finish; end end diff --git a/rtl/axis_async_fifo_adapter.v b/rtl/axis_async_fifo_adapter.v index d87e8108..a22f1cae 100644 --- a/rtl/axis_async_fifo_adapter.v +++ b/rtl/axis_async_fifo_adapter.v @@ -133,17 +133,17 @@ parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT; // bus width assertions initial begin if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin - $error("Error: input data width not evenly divisble"); + $error("Error: input data width not evenly divisble (instance %m)"); $finish; end if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin - $error("Error: output data width not evenly divisble"); + $error("Error: output data width not evenly divisble (instance %m)"); $finish; end if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin - $error("Error: word size mismatch"); + $error("Error: word size mismatch (instance %m)"); $finish; end end diff --git a/rtl/axis_fifo.v b/rtl/axis_fifo.v index 605fc192..d3b19adf 100644 --- a/rtl/axis_fifo.v +++ b/rtl/axis_fifo.v @@ -113,22 +113,22 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH // check configuration initial begin if (FRAME_FIFO && !LAST_ENABLE) begin - $error("Error: FRAME_FIFO set requires LAST_ENABLE set"); + $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); $finish; end if (DROP_BAD_FRAME && !FRAME_FIFO) begin - $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set"); + $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)"); $finish; end if (DROP_WHEN_FULL && !FRAME_FIFO) begin - $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set"); + $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)"); $finish; end if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin - $error("Error: Invalid USER_BAD_FRAME_MASK value"); + $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); $finish; end end diff --git a/rtl/axis_fifo_adapter.v b/rtl/axis_fifo_adapter.v index ae97f78f..94c390c9 100644 --- a/rtl/axis_fifo_adapter.v +++ b/rtl/axis_fifo_adapter.v @@ -129,17 +129,17 @@ parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT; // bus width assertions initial begin if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin - $error("Error: input data width not evenly divisble"); + $error("Error: input data width not evenly divisble (instance %m)"); $finish; end if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin - $error("Error: output data width not evenly divisble"); + $error("Error: output data width not evenly divisble (instance %m)"); $finish; end if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin - $error("Error: word size mismatch"); + $error("Error: word size mismatch (instance %m)"); $finish; end end diff --git a/rtl/axis_frame_length_adjust.v b/rtl/axis_frame_length_adjust.v index b7c21643..55257cb1 100644 --- a/rtl/axis_frame_length_adjust.v +++ b/rtl/axis_frame_length_adjust.v @@ -102,7 +102,7 @@ localparam DATA_WORD_WIDTH = DATA_WIDTH / KEEP_WIDTH; // bus width assertions initial begin if (DATA_WORD_WIDTH * KEEP_WIDTH != DATA_WIDTH) begin - $error("Error: data width not evenly divisble"); + $error("Error: data width not evenly divisble (instance %m)"); $finish; end end diff --git a/rtl/axis_switch.v b/rtl/axis_switch.v index 5352fe22..0e785851 100644 --- a/rtl/axis_switch.v +++ b/rtl/axis_switch.v @@ -113,7 +113,7 @@ integer i, j; // check configuration initial begin if (DEST_WIDTH < CL_M_COUNT) begin - $error("Error: DEST_WIDTH too small for port count"); + $error("Error: DEST_WIDTH too small for port count (instance %m)"); $finish; end @@ -126,7 +126,7 @@ initial begin if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] == M_BASE[j*DEST_WIDTH +: DEST_WIDTH]) begin $display("%d: %08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH]); $display("%d: %08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH]); - $error("Error: ranges overlap"); + $error("Error: ranges overlap (instance %m)"); $finish; end end @@ -134,7 +134,7 @@ initial begin end else begin for (i = 0; i < M_COUNT; i = i + 1) begin if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] > M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin - $error("Error: invalid range"); + $error("Error: invalid range (instance %m)"); $finish; end end @@ -144,7 +144,7 @@ initial begin if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[j*DEST_WIDTH +: DEST_WIDTH] && M_BASE[j*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin $display("%d: %08x-%08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH]); $display("%d: %08x-%08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH], M_TOP[j*DEST_WIDTH +: DEST_WIDTH]); - $error("Error: ranges overlap"); + $error("Error: ranges overlap (instance %m)"); $finish; end end From 6795c25e7ffd5d8380e3fc1f8b34e30179a24df7 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 9 Aug 2019 18:05:32 -0700 Subject: [PATCH 4/5] Fix use before define --- rtl/axis_cobs_encode.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/axis_cobs_encode.v b/rtl/axis_cobs_encode.v index 7a2d4b38..a0e24181 100644 --- a/rtl/axis_cobs_encode.v +++ b/rtl/axis_cobs_encode.v @@ -86,8 +86,6 @@ wire m_axis_tready_int_early; reg s_axis_tready_mask; -assign s_axis_tready = code_fifo_in_tready && data_fifo_in_tready && s_axis_tready_mask; - reg [7:0] code_fifo_in_tdata; reg code_fifo_in_tvalid; reg code_fifo_in_tlast; @@ -100,6 +98,8 @@ wire code_fifo_out_tlast; wire code_fifo_out_tuser; reg code_fifo_out_tready; +assign s_axis_tready = code_fifo_in_tready && data_fifo_in_tready && s_axis_tready_mask; + axis_fifo #( .DEPTH(256), .DATA_WIDTH(8), From a9c04a465150ae5fc9cd8f32906213d9ba9afb06 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 24 Oct 2019 12:08:08 -0700 Subject: [PATCH 5/5] Fix frame FIFO drop --- rtl/axis_async_fifo.v | 2 +- rtl/axis_fifo.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v index 416cc09c..39ac3498 100644 --- a/rtl/axis_async_fifo.v +++ b/rtl/axis_async_fifo.v @@ -280,7 +280,7 @@ end always @* begin write = 1'b0; - drop_frame_next = 1'b0; + drop_frame_next = drop_frame_reg; overflow_next = 1'b0; bad_frame_next = 1'b0; good_frame_next = 1'b0; diff --git a/rtl/axis_fifo.v b/rtl/axis_fifo.v index d3b19adf..93f41906 100644 --- a/rtl/axis_fifo.v +++ b/rtl/axis_fifo.v @@ -204,7 +204,7 @@ assign status_good_frame = good_frame_reg; always @* begin write = 1'b0; - drop_frame_next = 1'b0; + drop_frame_next = drop_frame_reg; overflow_next = 1'b0; bad_frame_next = 1'b0; good_frame_next = 1'b0;