Rename Arista_7132LB to DCS7132LB

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Signed-off-by: Alex Forencich <alex@alexforencich.com>

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Alex Forencich 2024-01-14 15:45:38 -08:00

parent dce0c92a57

commit a05d1a4550

17 changed files with 0 additions and 0 deletions

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example/Arista_7132LB/fpga_25g/README.md → example/DCS7132LB/fpga_25g/README.md

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example/Arista_7132LB/fpga_25g/common/vivado.mk → example/DCS7132LB/fpga_25g/common/vivado.mk

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example/Arista_7132LB/fpga_25g/fpga.xdc → example/DCS7132LB/fpga_25g/fpga.xdc

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example/Arista_7132LB/fpga_25g/fpga/Makefile → example/DCS7132LB/fpga_25g/fpga/Makefile

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example/Arista_7132LB/fpga_25g/fpga/config.tcl → example/DCS7132LB/fpga_25g/fpga/config.tcl

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example/Arista_7132LB/fpga_25g/fpga_10g/Makefile → example/DCS7132LB/fpga_25g/fpga_10g/Makefile

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example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl → example/DCS7132LB/fpga_25g/fpga_10g/config.tcl

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example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl → example/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl

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example/Arista_7132LB/fpga_25g/lib/eth → example/DCS7132LB/fpga_25g/lib/eth

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example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v → example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v

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example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v → example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v

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example/Arista_7132LB/fpga_25g/rtl/fpga.v → example/DCS7132LB/fpga_25g/rtl/fpga.v

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example/Arista_7132LB/fpga_25g/rtl/fpga_core.v → example/DCS7132LB/fpga_25g/rtl/fpga_core.v

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example/Arista_7132LB/fpga_25g/rtl/sync_signal.v → example/DCS7132LB/fpga_25g/rtl/sync_signal.v

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example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile → example/DCS7132LB/fpga_25g/tb/fpga_core/Makefile

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example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py → example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py

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example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v → example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v