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https://github.com/alexforencich/verilog-ethernet.git
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ISE does not support clog2 in localparam
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@ -87,8 +87,8 @@ module axis_baser_tx_64 #
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output wire error_underflow
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);
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localparam EMPTY_WIDTH = $clog2(KEEP_WIDTH);
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localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-KEEP_WIDTH+1);
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parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
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parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-KEEP_WIDTH+1);
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// bus width assertions
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initial begin
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@ -88,7 +88,7 @@ module axis_gmii_tx #
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output wire error_underflow
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);
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localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-1+1);
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parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-1+1);
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// bus width assertions
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initial begin
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@ -85,8 +85,8 @@ module axis_xgmii_tx_32 #
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output wire error_underflow
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);
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localparam EMPTY_WIDTH = $clog2(KEEP_WIDTH);
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localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
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parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
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parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
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// bus width assertions
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initial begin
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@ -87,8 +87,8 @@ module axis_xgmii_tx_64 #
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output wire error_underflow
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);
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localparam EMPTY_WIDTH = $clog2(KEEP_WIDTH);
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localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
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parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
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parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
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// bus width assertions
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initial begin
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