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Add cocotb testbenches for 10G MAC+PHY modules
This commit is contained in:
Alex Forencich
parent
e7dddc0dfd
commit
a539a76ec4
148
tb/eth_mac_phy_10g/Makefile
Normal file
148
tb/eth_mac_phy_10g/Makefile
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@ -0,0 +1,148 @@
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
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||||
#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = eth_mac_phy_10g
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TOPLEVEL = $(DUT)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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VERILOG_SOURCES += ../../rtl/$(DUT)_rx.v
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VERILOG_SOURCES += ../../rtl/$(DUT)_tx.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_if.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_ber_mon.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_frame_sync.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_tx_if.v
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VERILOG_SOURCES += ../../rtl/axis_baser_rx_64.v
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VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v
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VERILOG_SOURCES += ../../rtl/lfsr.v
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# module parameters
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export PARAM_DATA_WIDTH ?= 64
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export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
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export PARAM_HDR_WIDTH ?= 2
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export PARAM_ENABLE_PADDING ?= 1
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export PARAM_ENABLE_DIC ?= 1
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export PARAM_MIN_FRAME_LENGTH ?= 64
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export PARAM_PTP_PERIOD_NS ?= 6
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export PARAM_PTP_PERIOD_FNS ?= 26214
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export PARAM_TX_PTP_TS_ENABLE ?= 0
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export PARAM_TX_PTP_TS_WIDTH ?= 96
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export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE)
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export PARAM_TX_PTP_TAG_WIDTH ?= 16
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export PARAM_RX_PTP_TS_ENABLE ?= 0
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export PARAM_RX_PTP_TS_WIDTH ?= 96
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# export PARAM_TX_USER_WIDTH ?= (parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + 1
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export PARAM_TX_USER_WIDTH ?= 1
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# export PARAM_RX_USER_WIDTH ?= (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1
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export PARAM_RX_USER_WIDTH ?= 1
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export PARAM_BIT_REVERSE ?= 0
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export PARAM_SCRAMBLER_DISABLE ?= 0
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export PARAM_PRBS31_ENABLE ?= 1
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export PARAM_TX_SERDES_PIPELINE ?= 2
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export PARAM_RX_SERDES_PIPELINE ?= 2
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export PARAM_BITSLIP_HIGH_CYCLES ?= 1
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export PARAM_BITSLIP_LOW_CYCLES ?= 8
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export PARAM_COUNT_125US ?= 195
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING)
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COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC)
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COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH)
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COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS)
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COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS)
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COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).TX_USER_WIDTH=$(PARAM_TX_USER_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).RX_USER_WIDTH=$(PARAM_RX_USER_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).BIT_REVERSE=$(PARAM_BIT_REVERSE)
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COMPILE_ARGS += -P $(TOPLEVEL).SCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).PRBS31_ENABLE=$(PARAM_PRBS31_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).TX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE)
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COMPILE_ARGS += -P $(TOPLEVEL).RX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE)
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COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES)
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COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES)
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COMPILE_ARGS += -P $(TOPLEVEL).COUNT_125US=$(PARAM_COUNT_125US)
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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COMPILE_ARGS += -s iverilog_dump
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endif
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
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COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH)
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COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH)
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COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING)
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COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC)
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COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH)
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COMPILE_ARGS += -GPTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS)
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COMPILE_ARGS += -GPTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS)
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COMPILE_ARGS += -GTX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE)
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COMPILE_ARGS += -GTX_PTP_TS_WIDTH=$(PARAM_TX_PTP_TS_WIDTH)
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COMPILE_ARGS += -GTX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE)
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COMPILE_ARGS += -GTX_PTP_TAG_WIDTH=$(PARAM_TX_PTP_TAG_WIDTH)
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COMPILE_ARGS += -GRX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE)
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COMPILE_ARGS += -GRX_PTP_TS_WIDTH=$(PARAM_RX_PTP_TS_WIDTH)
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COMPILE_ARGS += -GTX_USER_WIDTH=$(PARAM_TX_USER_WIDTH)
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COMPILE_ARGS += -GRX_USER_WIDTH=$(PARAM_RX_USER_WIDTH)
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COMPILE_ARGS += -GBIT_REVERSE=$(PARAM_BIT_REVERSE)
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COMPILE_ARGS += -GSCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE)
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COMPILE_ARGS += -GPRBS31_ENABLE=$(PARAM_PRBS31_ENABLE)
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COMPILE_ARGS += -GTX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE)
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COMPILE_ARGS += -GRX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE)
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COMPILE_ARGS += -GBITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES)
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COMPILE_ARGS += -GBITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES)
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COMPILE_ARGS += -GCOUNT_125US=$(PARAM_COUNT_125US)
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
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echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
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echo 'end' >> $@
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echo 'endmodule' >> $@
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clean::
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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1
tb/eth_mac_phy_10g/baser.py
Symbolic link
1
tb/eth_mac_phy_10g/baser.py
Symbolic link
@ -0,0 +1 @@
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../baser.py
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361
tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
Normal file
361
tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
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@ -0,0 +1,361 @@
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#!/usr/bin/env python
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"""
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
|
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in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import sys
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import pytest
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.eth import XgmiiFrame
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from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
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try:
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from baser import BaseRSerdesSource, BaseRSerdesSink
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except ImportError:
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# attempt import from current directory
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sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
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try:
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from baser import BaseRSerdesSource, BaseRSerdesSink
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finally:
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del sys.path[0]
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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if len(dut.serdes_tx_data) == 64:
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cocotb.fork(Clock(dut.rx_clk, 6.4, units="ns").start())
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cocotb.fork(Clock(dut.tx_clk, 6.4, units="ns").start())
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else:
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cocotb.fork(Clock(dut.rx_clk, 3.2, units="ns").start())
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cocotb.fork(Clock(dut.tx_clk, 3.2, units="ns").start())
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self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
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self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk)
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self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst)
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self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
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dut.rx_ptp_ts.setimmediatevalue(0)
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dut.tx_ptp_ts.setimmediatevalue(0)
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dut.tx_prbs31_enable.setimmediatevalue(0)
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dut.rx_prbs31_enable.setimmediatevalue(0)
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async def reset(self):
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self.dut.rx_rst.setimmediatevalue(0)
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self.dut.tx_rst.setimmediatevalue(0)
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await RisingEdge(self.dut.rx_clk)
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await RisingEdge(self.dut.rx_clk)
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self.dut.rx_rst <= 1
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self.dut.tx_rst <= 1
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await RisingEdge(self.dut.rx_clk)
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await RisingEdge(self.dut.rx_clk)
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self.dut.rx_rst <= 0
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self.dut.tx_rst <= 0
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await RisingEdge(self.dut.rx_clk)
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await RisingEdge(self.dut.rx_clk)
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async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
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tb = TB(dut)
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tb.serdes_source.ifg = ifg
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tb.dut.ifg_delay <= ifg
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await tb.reset()
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tb.log.info("Wait for block lock")
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while not dut.rx_block_lock.value.integer:
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await RisingEdge(dut.rx_clk)
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# clear out sink buffer
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tb.axis_sink.clear()
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test_frames = [payload_data(x) for x in payload_lengths()]
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for test_data in test_frames:
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test_frame = XgmiiFrame.from_payload(test_data)
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await tb.serdes_source.send(test_frame)
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for test_data in test_frames:
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rx_frame = await tb.axis_sink.recv()
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assert rx_frame.tdata == test_data
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assert rx_frame.tuser == 0
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assert tb.axis_sink.empty()
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await RisingEdge(dut.rx_clk)
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await RisingEdge(dut.rx_clk)
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async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
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tb = TB(dut)
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tb.serdes_source.ifg = ifg
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tb.dut.ifg_delay <= ifg
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await tb.reset()
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test_frames = [payload_data(x) for x in payload_lengths()]
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for test_data in test_frames:
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await tb.axis_source.send(test_data)
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for test_data in test_frames:
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rx_frame = await tb.serdes_sink.recv()
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assert rx_frame.get_payload() == test_data
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assert rx_frame.check_fcs()
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assert tb.serdes_sink.empty()
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await RisingEdge(dut.tx_clk)
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await RisingEdge(dut.tx_clk)
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async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
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enable_dic = int(os.getenv("PARAM_ENABLE_DIC"))
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tb = TB(dut)
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byte_width = tb.axis_source.width // 8
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tb.serdes_source.ifg = ifg
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tb.dut.ifg_delay <= ifg
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for length in range(60, 92):
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await tb.reset()
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test_frames = [payload_data(length) for k in range(10)]
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start_lane = []
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for test_data in test_frames:
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await tb.axis_source.send(test_data)
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for test_data in test_frames:
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rx_frame = await tb.serdes_sink.recv()
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assert rx_frame.get_payload() == test_data
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assert rx_frame.check_fcs()
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assert rx_frame.ctrl is None
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start_lane.append(rx_frame.start_lane)
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tb.log.info("length: %d", length)
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tb.log.info("start_lane: %s", start_lane)
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start_lane_ref = []
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# compute expected starting lanes
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lane = 0
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deficit_idle_count = 0
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for test_data in test_frames:
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if ifg == 0:
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lane = 0
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start_lane_ref.append(lane)
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lane = (lane + len(test_data)+4+ifg) % byte_width
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if enable_dic:
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offset = lane % 4
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if deficit_idle_count+offset >= 4:
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offset += 4
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lane = (lane - offset) % byte_width
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deficit_idle_count = (deficit_idle_count + offset) % 4
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else:
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offset = lane % 4
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if offset > 0:
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offset += 4
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lane = (lane - offset) % byte_width
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tb.log.info("start_lane_ref: %s", start_lane_ref)
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assert start_lane_ref == start_lane
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await RisingEdge(dut.tx_clk)
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assert tb.serdes_sink.empty()
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await RisingEdge(dut.tx_clk)
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await RisingEdge(dut.tx_clk)
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async def run_test_rx_frame_sync(dut):
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tb = TB(dut)
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await tb.reset()
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tb.log.info("Wait for block lock")
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while not dut.rx_block_lock.value.integer:
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await RisingEdge(dut.rx_clk)
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assert dut.rx_block_lock.value.integer
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tb.log.info("Change offset")
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tb.serdes_source.bit_offset = 33
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for k in range(100):
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await RisingEdge(dut.rx_clk)
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tb.log.info("Check for lock lost")
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assert not dut.rx_block_lock.value.integer
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assert dut.rx_high_ber.value.integer
|
||||
|
||||
for k in range(500):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.log.info("Check for block lock")
|
||||
assert dut.rx_block_lock.value.integer
|
||||
|
||||
for k in range(300):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.log.info("Check for high BER deassert")
|
||||
assert not dut.rx_high_ber.value.integer
|
||||
|
||||
await RisingEdge(dut.rx_clk)
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def cycle_en():
|
||||
return itertools.cycle([0, 0, 0, 1])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_rx, run_test_tx]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("ifg", [12, 0])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_test_tx_alignment)
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("ifg", [12])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_test_rx_frame_sync)
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
|
||||
|
||||
@pytest.mark.parametrize("enable_dic", [1, 0])
|
||||
@pytest.mark.parametrize("data_width", [64])
|
||||
def test_eth_mac_phy_10g(request, data_width, enable_dic):
|
||||
dut = "eth_mac_phy_10g"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, f"{dut}_rx.v"),
|
||||
os.path.join(rtl_dir, f"{dut}_tx.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_rx_if.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_rx_ber_mon.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_rx_frame_sync.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_tx_if.v"),
|
||||
os.path.join(rtl_dir, "axis_baser_rx_64.v"),
|
||||
os.path.join(rtl_dir, "axis_baser_tx_64.v"),
|
||||
os.path.join(rtl_dir, "lfsr.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_WIDTH'] = data_width
|
||||
parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
|
||||
parameters['HDR_WIDTH'] = 2
|
||||
parameters['ENABLE_PADDING'] = 1
|
||||
parameters['ENABLE_DIC'] = enable_dic
|
||||
parameters['MIN_FRAME_LENGTH'] = 64
|
||||
parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3
|
||||
parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333
|
||||
parameters['TX_PTP_TS_ENABLE'] = 0
|
||||
parameters['TX_PTP_TS_WIDTH'] = 96
|
||||
parameters['TX_PTP_TAG_ENABLE'] = parameters['TX_PTP_TS_ENABLE']
|
||||
parameters['TX_PTP_TAG_WIDTH'] = 16
|
||||
parameters['RX_PTP_TS_ENABLE'] = 0
|
||||
parameters['RX_PTP_TS_WIDTH'] = 96
|
||||
parameters['TX_USER_WIDTH'] = (parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TS_ENABLE'] and parameters['TX_PTP_TAG_ENABLE'] else 0) + 1
|
||||
parameters['RX_USER_WIDTH'] = (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1
|
||||
parameters['BIT_REVERSE'] = 0
|
||||
parameters['SCRAMBLER_DISABLE'] = 0
|
||||
parameters['PRBS31_ENABLE'] = 1
|
||||
parameters['TX_SERDES_PIPELINE'] = 2
|
||||
parameters['RX_SERDES_PIPELINE'] = 2
|
||||
parameters['BITSLIP_HIGH_CYCLES'] = 1
|
||||
parameters['BITSLIP_LOW_CYCLES'] = 8
|
||||
parameters['COUNT_125US'] = int(1250/6.4)
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
197
tb/eth_mac_phy_10g_fifo/Makefile
Normal file
197
tb/eth_mac_phy_10g_fifo/Makefile
Normal file
@ -0,0 +1,197 @@
|
||||
# Copyright (c) 2021 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = eth_mac_phy_10g_fifo
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/eth_mac_phy_10g.v
|
||||
VERILOG_SOURCES += ../../rtl/eth_mac_phy_10g_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/eth_mac_phy_10g_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_if.v
|
||||
VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_ber_mon.v
|
||||
VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_frame_sync.v
|
||||
VERILOG_SOURCES += ../../rtl/eth_phy_10g_tx_if.v
|
||||
VERILOG_SOURCES += ../../rtl/axis_baser_rx_64.v
|
||||
VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v
|
||||
VERILOG_SOURCES += ../../rtl/lfsr.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_WIDTH ?= 64
|
||||
export PARAM_HDR_WIDTH ?= 2
|
||||
export PARAM_AXIS_DATA_WIDTH ?= $(PARAM_DATA_WIDTH)
|
||||
export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 )
|
||||
export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 )
|
||||
export PARAM_ENABLE_PADDING ?= 1
|
||||
export PARAM_ENABLE_DIC ?= 1
|
||||
export PARAM_MIN_FRAME_LENGTH ?= 64
|
||||
export PARAM_TX_FIFO_DEPTH ?= 16384
|
||||
export PARAM_TX_FIFO_PIPELINE_OUTPUT ?= 2
|
||||
export PARAM_TX_FRAME_FIFO ?= 1
|
||||
export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO)
|
||||
export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_TX_DROP_WHEN_FULL ?= 0
|
||||
export PARAM_RX_FIFO_DEPTH ?= 16384
|
||||
export PARAM_RX_FIFO_PIPELINE_OUTPUT ?= 2
|
||||
export PARAM_RX_FRAME_FIFO ?= 1
|
||||
export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO)
|
||||
export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_PTP_PERIOD_NS ?= 6
|
||||
export PARAM_PTP_PERIOD_FNS ?= 26214
|
||||
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
|
||||
export PARAM_TX_PTP_TS_ENABLE ?= 0
|
||||
export PARAM_RX_PTP_TS_ENABLE ?= 0
|
||||
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 64
|
||||
export PARAM_PTP_TS_WIDTH ?= 96
|
||||
export PARAM_TX_PTP_TAG_ENABLE ?= 0
|
||||
export PARAM_PTP_TAG_WIDTH ?= 16
|
||||
# export PARAM_TX_USER_WIDTH ?= (parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + 1
|
||||
export PARAM_TX_USER_WIDTH ?= 1
|
||||
# export PARAM_RX_USER_WIDTH ?= (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1
|
||||
export PARAM_RX_USER_WIDTH ?= 1
|
||||
export PARAM_BIT_REVERSE ?= 0
|
||||
export PARAM_SCRAMBLER_DISABLE ?= 0
|
||||
export PARAM_PRBS31_ENABLE ?= 1
|
||||
export PARAM_TX_SERDES_PIPELINE ?= 2
|
||||
export PARAM_RX_SERDES_PIPELINE ?= 2
|
||||
export PARAM_BITSLIP_HIGH_CYCLES ?= 1
|
||||
export PARAM_BITSLIP_LOW_CYCLES ?= 8
|
||||
export PARAM_COUNT_125US ?= 195
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).HDR_WIDTH=$(PARAM_HDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_PADDING=$(PARAM_ENABLE_PADDING)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_PIPELINE_OUTPUT=$(PARAM_TX_FIFO_PIPELINE_OUTPUT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_PIPELINE_OUTPUT=$(PARAM_RX_FIFO_PIPELINE_OUTPUT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_USER_WIDTH=$(PARAM_TX_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_USER_WIDTH=$(PARAM_RX_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BIT_REVERSE=$(PARAM_BIT_REVERSE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PRBS31_ENABLE=$(PARAM_PRBS31_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).COUNT_125US=$(PARAM_COUNT_125US)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GHDR_WIDTH=$(PARAM_HDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_KEEP_ENABLE=$(PARAM_AXIS_KEEP_ENABLE)
|
||||
COMPILE_ARGS += -GAXIS_KEEP_WIDTH=$(PARAM_AXIS_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -GENABLE_PADDING=$(PARAM_ENABLE_PADDING)
|
||||
COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC)
|
||||
COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_FIFO_PIPELINE_OUTPUT=$(PARAM_TX_FIFO_PIPELINE_OUTPUT)
|
||||
COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO)
|
||||
COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME)
|
||||
COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME)
|
||||
COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_PIPELINE_OUTPUT=$(PARAM_RX_FIFO_PIPELINE_OUTPUT)
|
||||
COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO)
|
||||
COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME)
|
||||
COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME)
|
||||
COMPILE_ARGS += -GRX_DROP_WHEN_FULL=$(PARAM_RX_DROP_WHEN_FULL)
|
||||
COMPILE_ARGS += -GPTP_PERIOD_NS=$(PARAM_PTP_PERIOD_NS)
|
||||
COMPILE_ARGS += -GPTP_PERIOD_FNS=$(PARAM_PTP_PERIOD_FNS)
|
||||
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -GTX_PTP_TS_ENABLE=$(PARAM_TX_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_PTP_TS_ENABLE=$(PARAM_RX_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GPTP_TS_WIDTH=$(PARAM_PTP_TS_WIDTH)
|
||||
COMPILE_ARGS += -GTX_PTP_TAG_ENABLE=$(PARAM_TX_PTP_TAG_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_TAG_WIDTH=$(PARAM_PTP_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GTX_USER_WIDTH=$(PARAM_TX_USER_WIDTH)
|
||||
COMPILE_ARGS += -GRX_USER_WIDTH=$(PARAM_RX_USER_WIDTH)
|
||||
COMPILE_ARGS += -GBIT_REVERSE=$(PARAM_BIT_REVERSE)
|
||||
COMPILE_ARGS += -GSCRAMBLER_DISABLE=$(PARAM_SCRAMBLER_DISABLE)
|
||||
COMPILE_ARGS += -GPRBS31_ENABLE=$(PARAM_PRBS31_ENABLE)
|
||||
COMPILE_ARGS += -GTX_SERDES_PIPELINE=$(PARAM_TX_SERDES_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_SERDES_PIPELINE=$(PARAM_RX_SERDES_PIPELINE)
|
||||
COMPILE_ARGS += -GBITSLIP_HIGH_CYCLES=$(PARAM_BITSLIP_HIGH_CYCLES)
|
||||
COMPILE_ARGS += -GBITSLIP_LOW_CYCLES=$(PARAM_BITSLIP_LOW_CYCLES)
|
||||
COMPILE_ARGS += -GCOUNT_125US=$(PARAM_COUNT_125US)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
1
tb/eth_mac_phy_10g_fifo/baser.py
Symbolic link
1
tb/eth_mac_phy_10g_fifo/baser.py
Symbolic link
@ -0,0 +1 @@
|
||||
../baser.py
|
||||
386
tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
Normal file
386
tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
Normal file
@ -0,0 +1,386 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import pytest
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.eth import XgmiiFrame
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
|
||||
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
if len(dut.serdes_tx_data) == 64:
|
||||
cocotb.fork(Clock(dut.logic_clk, 6.4, units="ns").start())
|
||||
cocotb.fork(Clock(dut.rx_clk, 6.4, units="ns").start())
|
||||
cocotb.fork(Clock(dut.tx_clk, 6.4, units="ns").start())
|
||||
else:
|
||||
cocotb.fork(Clock(dut.logic_clk, 3.2, units="ns").start())
|
||||
cocotb.fork(Clock(dut.rx_clk, 3.2, units="ns").start())
|
||||
cocotb.fork(Clock(dut.tx_clk, 3.2, units="ns").start())
|
||||
|
||||
self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
|
||||
self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk)
|
||||
|
||||
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.logic_clk, dut.logic_rst)
|
||||
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst)
|
||||
|
||||
dut.ptp_sample_clk.setimmediatevalue(0)
|
||||
dut.ptp_ts_96.setimmediatevalue(0)
|
||||
dut.ptp_ts_step.setimmediatevalue(0)
|
||||
|
||||
dut.tx_prbs31_enable.setimmediatevalue(0)
|
||||
dut.rx_prbs31_enable.setimmediatevalue(0)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.logic_rst.setimmediatevalue(0)
|
||||
self.dut.rx_rst.setimmediatevalue(0)
|
||||
self.dut.tx_rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
self.dut.logic_rst <= 1
|
||||
self.dut.rx_rst <= 1
|
||||
self.dut.tx_rst <= 1
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
self.dut.logic_rst <= 0
|
||||
self.dut.rx_rst <= 0
|
||||
self.dut.tx_rst <= 0
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
|
||||
|
||||
async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.ifg_delay <= ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not dut.rx_block_lock.value.integer:
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
# clear out sink buffer
|
||||
tb.axis_sink.clear()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = XgmiiFrame.from_payload(test_data)
|
||||
await tb.serdes_source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.axis_sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser == 0
|
||||
|
||||
assert tb.axis_sink.empty()
|
||||
|
||||
await RisingEdge(dut.logic_clk)
|
||||
await RisingEdge(dut.logic_clk)
|
||||
|
||||
|
||||
async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.ifg_delay <= ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
await tb.axis_source.send(test_data)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.serdes_sink.recv()
|
||||
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
await RisingEdge(dut.logic_clk)
|
||||
await RisingEdge(dut.logic_clk)
|
||||
|
||||
|
||||
async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
|
||||
|
||||
enable_dic = int(os.getenv("PARAM_ENABLE_DIC"))
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_width = tb.axis_source.width // 8
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.ifg_delay <= ifg
|
||||
|
||||
for length in range(60, 92):
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = [payload_data(length) for k in range(10)]
|
||||
start_lane = []
|
||||
|
||||
for test_data in test_frames:
|
||||
await tb.axis_source.send(test_data)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.serdes_sink.recv()
|
||||
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.ctrl is None
|
||||
|
||||
start_lane.append(rx_frame.start_lane)
|
||||
|
||||
tb.log.info("length: %d", length)
|
||||
tb.log.info("start_lane: %s", start_lane)
|
||||
|
||||
start_lane_ref = []
|
||||
|
||||
# compute expected starting lanes
|
||||
lane = 0
|
||||
deficit_idle_count = 0
|
||||
|
||||
for test_data in test_frames:
|
||||
if ifg == 0:
|
||||
lane = 0
|
||||
|
||||
start_lane_ref.append(lane)
|
||||
lane = (lane + len(test_data)+4+ifg) % byte_width
|
||||
|
||||
if enable_dic:
|
||||
offset = lane % 4
|
||||
if deficit_idle_count+offset >= 4:
|
||||
offset += 4
|
||||
lane = (lane - offset) % byte_width
|
||||
deficit_idle_count = (deficit_idle_count + offset) % 4
|
||||
else:
|
||||
offset = lane % 4
|
||||
if offset > 0:
|
||||
offset += 4
|
||||
lane = (lane - offset) % byte_width
|
||||
|
||||
tb.log.info("start_lane_ref: %s", start_lane_ref)
|
||||
|
||||
assert start_lane_ref == start_lane
|
||||
|
||||
await RisingEdge(dut.logic_clk)
|
||||
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
await RisingEdge(dut.logic_clk)
|
||||
await RisingEdge(dut.logic_clk)
|
||||
|
||||
|
||||
async def run_test_rx_frame_sync(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not dut.rx_block_lock.value.integer:
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
assert dut.rx_block_lock.value.integer
|
||||
|
||||
tb.log.info("Change offset")
|
||||
tb.serdes_source.bit_offset = 33
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.log.info("Check for lock lost")
|
||||
assert not dut.rx_block_lock.value.integer
|
||||
assert dut.rx_high_ber.value.integer
|
||||
|
||||
for k in range(500):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.log.info("Check for block lock")
|
||||
assert dut.rx_block_lock.value.integer
|
||||
|
||||
for k in range(300):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.log.info("Check for high BER deassert")
|
||||
assert not dut.rx_high_ber.value.integer
|
||||
|
||||
await RisingEdge(dut.rx_clk)
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def cycle_en():
|
||||
return itertools.cycle([0, 0, 0, 1])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_rx, run_test_tx]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("ifg", [12, 0])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_test_tx_alignment)
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("ifg", [12])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_test_rx_frame_sync)
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
|
||||
|
||||
@pytest.mark.parametrize("enable_dic", [1, 0])
|
||||
@pytest.mark.parametrize("data_width", [64])
|
||||
def test_eth_mac_phy_10g_fifo(request, data_width, enable_dic):
|
||||
dut = "eth_mac_phy_10g_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "eth_mac_phy_10g.v"),
|
||||
os.path.join(rtl_dir, "eth_mac_phy_10g_rx.v"),
|
||||
os.path.join(rtl_dir, "eth_mac_phy_10g_tx.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_rx_if.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_rx_ber_mon.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_rx_frame_sync.v"),
|
||||
os.path.join(rtl_dir, "eth_phy_10g_tx_if.v"),
|
||||
os.path.join(rtl_dir, "axis_baser_rx_64.v"),
|
||||
os.path.join(rtl_dir, "axis_baser_tx_64.v"),
|
||||
os.path.join(rtl_dir, "lfsr.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_WIDTH'] = data_width
|
||||
parameters['HDR_WIDTH'] = 2
|
||||
parameters['AXIS_DATA_WIDTH'] = parameters['DATA_WIDTH']
|
||||
parameters['AXIS_KEEP_ENABLE'] = int(parameters['AXIS_DATA_WIDTH'] > 8)
|
||||
parameters['AXIS_KEEP_WIDTH'] = parameters['AXIS_DATA_WIDTH'] // 8
|
||||
parameters['ENABLE_PADDING'] = 1
|
||||
parameters['ENABLE_DIC'] = enable_dic
|
||||
parameters['MIN_FRAME_LENGTH'] = 64
|
||||
parameters['TX_FIFO_DEPTH'] = 16384
|
||||
parameters['TX_FIFO_PIPELINE_OUTPUT'] = 2
|
||||
parameters['TX_FRAME_FIFO'] = 1
|
||||
parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
|
||||
parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
|
||||
parameters['TX_DROP_WHEN_FULL'] = 0
|
||||
parameters['RX_FIFO_DEPTH'] = 16384
|
||||
parameters['RX_FIFO_PIPELINE_OUTPUT'] = 2
|
||||
parameters['RX_FRAME_FIFO'] = 1
|
||||
parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
|
||||
parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
|
||||
parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
|
||||
parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3
|
||||
parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333
|
||||
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
|
||||
parameters['TX_PTP_TS_ENABLE'] = 0
|
||||
parameters['RX_PTP_TS_ENABLE'] = 0
|
||||
parameters['TX_PTP_TS_FIFO_DEPTH'] = 64
|
||||
parameters['PTP_TS_WIDTH'] = 96
|
||||
parameters['TX_PTP_TAG_ENABLE'] = 0
|
||||
parameters['PTP_TAG_WIDTH'] = 16
|
||||
parameters['TX_USER_WIDTH'] = (parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TS_ENABLE'] and parameters['TX_PTP_TAG_ENABLE'] else 0) + 1
|
||||
parameters['RX_USER_WIDTH'] = (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1
|
||||
parameters['BIT_REVERSE'] = 0
|
||||
parameters['SCRAMBLER_DISABLE'] = 0
|
||||
parameters['PRBS31_ENABLE'] = 1
|
||||
parameters['TX_SERDES_PIPELINE'] = 2
|
||||
parameters['RX_SERDES_PIPELINE'] = 2
|
||||
parameters['BITSLIP_HIGH_CYCLES'] = 1
|
||||
parameters['BITSLIP_LOW_CYCLES'] = 8
|
||||
parameters['COUNT_125US'] = int(1250/6.4)
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user