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Fix generate statement

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This commit is contained in:
Alex Forencich 2018-11-28 14:18:09 -08:00
parent 8d564b1074
commit a72d7bd260
1 changed files with 3 additions and 3 deletions
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6
rtl/axis_pipeline_register.v
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@ -100,10 +100,10 @@ assign m_axis_tid = axis_tid[LENGTH];
assign m_axis_tdest = axis_tdest[LENGTH];
assign m_axis_tuser = axis_tuser[LENGTH];
integer i;
generate
for (i = 0; i < LENGTH; i = i + 1) begin : reg
genvar i;
for (i = 0; i < LENGTH; i = i + 1) begin : pipe_reg
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),