Update Atlys example design

example/ATLYS/fpga/clock.ucf

@@ -1,6 +1,6 @@
 # UCF file for clock module domain crossing constraints
 
 NET "clk_int" TNM = "ffs_clk_int";
-NET "core_inst/gmii_rx_clk" TNM = "ffs_gmii_rx_clk";
+NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk";
 TIMESPEC "TS_clk_int_to_gmii_rx_clk" = FROM "ffs_clk_int" TO "ffs_gmii_rx_clk" 10 ns;
 TIMESPEC "TS_gmii_rx_clk_to_clk_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_int" 10 ns;

example/ATLYS/fpga/fpga.ucf

@@ -45,6 +45,7 @@ NET "phy_reset_n" LOC = "G13" | IOSTANDARD=LVCMOS25; # IO_L32N_A16_M1A9 (E-RESET
 #NET "phy_mdio" LOC = "N17" | IOSTANDARD=LVCMOS25; # IO_L48P_HDC_M1DQ8 (E-MDIO)
 # GMII Transmit
 NET "phy_gtx_clk" LOC = "L12" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L40P_GCLK11_M1A5 (E-GTXCLK)
+NET "phy_tx_clk"  LOC = "K16" | IOSTANDARD=LVCMOS25; # IO_L41N_GCLK8_M1CASN (E-TXCLK)
 NET "phy_txd<0>"  LOC = "H16" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L37N_A6_M1A1 (E-TXD0)
 NET "phy_txd<1>"  LOC = "H13" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L36P_A9_M1BA0 (E-TXD1)
 NET "phy_txd<2>"  LOC = "K14" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L39N_M1ODT (E-TXD2)
@@ -55,7 +56,7 @@ NET "phy_txd<6>" LOC = "H12" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L32P_A17_
 NET "phy_txd<7>"  LOC = "K12" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L34P_A13_M1WE (E-TXD7)
 NET "phy_tx_en"   LOC = "H15" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L37P_A7_M1A0 (E-TXEN)
 NET "phy_tx_er"   LOC = "G18" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # IO_L38N_A4_M1CLKN (E-TXER)
-# GMII Receive (not used)
+# GMII Receive
 NET "phy_rx_clk"  LOC = "K15" | IOSTANDARD=LVCMOS25 | TNM_NET = "clk_rx_local"; # IO_L41P_GCLK9_IRDY1_M1RASN (E-RXCLK)
 NET "phy_rxd<0>"  LOC = "G16" | IOSTANDARD=LVCMOS25; # IO_L38P_A5_M1CLK (E-RXD0)
 NET "phy_rxd<1>"  LOC = "H14" | IOSTANDARD=LVCMOS25; # IO_L36N_A8_M1BA1 (E-RXD1)

example/ATLYS/fpga/fpga/Makefile

@@ -19,10 +19,11 @@ SYN_FILES += lib/eth/rtl/oddr.v
 SYN_FILES += lib/eth/rtl/ssio_sdr_in.v
 SYN_FILES += lib/eth/rtl/ssio_sdr_out.v
 SYN_FILES += lib/eth/rtl/gmii_phy_if.v
-SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii.v
 SYN_FILES += lib/eth/rtl/eth_mac_1g.v
-SYN_FILES += lib/eth/rtl/eth_mac_1g_rx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
-SYN_FILES += lib/eth/rtl/eth_mac_1g_tx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/eth_axis_rx.v
 SYN_FILES += lib/eth/rtl/eth_axis_tx.v

example/ATLYS/fpga/rtl/fpga.v

@@ -56,6 +56,7 @@ module fpga (
     input  wire       phy_rx_dv,
     input  wire       phy_rx_er,
     output wire       phy_gtx_clk,
+    input  wire       phy_tx_clk,
     output wire [7:0] phy_txd,
     output wire       phy_tx_en,
     output wire       phy_tx_er,
@@ -205,6 +206,7 @@ core_inst (
     .phy_rx_dv(phy_rx_dv),
     .phy_rx_er(phy_rx_er),
     .phy_gtx_clk(phy_gtx_clk),
+    .phy_tx_clk(phy_tx_clk),
     .phy_txd(phy_txd),
     .phy_tx_en(phy_tx_en),
     .phy_tx_er(phy_tx_er),

example/ATLYS/fpga/rtl/fpga_core.v

@@ -60,6 +60,7 @@ module fpga_core #
     input  wire       phy_rx_dv,
     input  wire       phy_rx_er,
     output wire       phy_gtx_clk,
+    input  wire       phy_tx_clk,
     output wire [7:0] phy_txd,
     output wire       phy_tx_en,
     output wire       phy_tx_er,
@@ -72,19 +73,6 @@ module fpga_core #
     output wire       uart_txd
 );
 
-// GMII between MAC and PHY IF
-wire gmii_rx_clk;
-wire gmii_rx_rst;
-wire [7:0] gmii_rxd;
-wire gmii_rx_dv;
-wire gmii_rx_er;
-
-wire gmii_tx_clk;
-wire gmii_tx_rst;
-wire [7:0] gmii_txd;
-wire gmii_tx_en;
-wire gmii_tx_er;
-
 // AXI between MAC and Ethernet modules
 wire [7:0] rx_axis_tdata;
 wire rx_axis_tvalid;
@@ -322,47 +310,18 @@ assign phy_reset_n = ~rst;
 
 assign uart_txd = 0;
 
-gmii_phy_if #(
+eth_mac_1g_gmii_fifo #(
     .TARGET(TARGET),
     .IODDR_STYLE("IODDR2"),
-    .CLOCK_INPUT_STYLE("BUFIO2")
+    .CLOCK_INPUT_STYLE("BUFIO2"),
-)
-gmii_phy_if_inst (
-    .clk(clk),
-    .rst(rst),
-
-    .mac_gmii_rx_clk(gmii_rx_clk),
-    .mac_gmii_rx_rst(gmii_rx_rst),
-    .mac_gmii_rxd(gmii_rxd),
-    .mac_gmii_rx_dv(gmii_rx_dv),
-    .mac_gmii_rx_er(gmii_rx_er),
-    .mac_gmii_tx_clk(gmii_tx_clk),
-    .mac_gmii_tx_rst(gmii_tx_rst),
-    .mac_gmii_txd(gmii_txd),
-    .mac_gmii_tx_en(gmii_tx_en),
-    .mac_gmii_tx_er(gmii_tx_er),
-
-    .phy_gmii_rx_clk(phy_rx_clk),
-    .phy_gmii_rxd(phy_rxd),
-    .phy_gmii_rx_dv(phy_rx_dv),
-    .phy_gmii_rx_er(phy_rx_er),
-    .phy_gmii_tx_clk(phy_gtx_clk),
-    .phy_gmii_txd(phy_txd),
-    .phy_gmii_tx_en(phy_tx_en),
-    .phy_gmii_tx_er(phy_tx_er)
-);
-
-eth_mac_1g_fifo #(
     .ENABLE_PADDING(1),
     .MIN_FRAME_LENGTH(64),
     .TX_FIFO_ADDR_WIDTH(12),
     .RX_FIFO_ADDR_WIDTH(12)
 )
-eth_mac_1g_fifo_inst (
+eth_mac_inst (
-    .rx_clk(gmii_rx_clk),
+    .gtx_clk(clk),
-    .rx_rst(gmii_rx_rst),
+    .gtx_rst(rst),
-    .tx_clk(gmii_tx_clk),
-    .tx_rst(gmii_tx_rst),
     .logic_clk(clk),
     .logic_rst(rst),
 
@@ -378,15 +337,25 @@ eth_mac_1g_fifo_inst (
     .rx_axis_tlast(rx_axis_tlast),
     .rx_axis_tuser(rx_axis_tuser),
 
-    .gmii_rxd(gmii_rxd),
+    .gmii_rx_clk(phy_rx_clk),
-    .gmii_rx_dv(gmii_rx_dv),
+    .gmii_rxd(phy_rxd),
-    .gmii_rx_er(gmii_rx_er),
+    .gmii_rx_dv(phy_rx_dv),
-    .gmii_txd(gmii_txd),
+    .gmii_rx_er(phy_rx_er),
-    .gmii_tx_en(gmii_tx_en),
+    .gmii_tx_clk(phy_gtx_clk),
-    .gmii_tx_er(gmii_tx_er),
+    .mii_tx_clk(phy_tx_clk),
+    .gmii_txd(phy_txd),
+    .gmii_tx_en(phy_tx_en),
+    .gmii_tx_er(phy_tx_er),
 
+    .tx_fifo_overflow(),
+    .tx_fifo_bad_frame(),
+    .tx_fifo_good_frame(),
     .rx_error_bad_frame(rx_error_bad_frame),
     .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_fifo_overflow(),
+    .rx_fifo_bad_frame(),
+    .rx_fifo_good_frame(),
+    .speed(),
 
     .ifg_delay(12)
 );

example/ATLYS/fpga/tb/test_fpga_core.py

@@ -42,10 +42,11 @@ srcs.append("../lib/eth/rtl/oddr.v")
 srcs.append("../lib/eth/rtl/ssio_sdr_in.v")
 srcs.append("../lib/eth/rtl/ssio_sdr_out.v")
 srcs.append("../lib/eth/rtl/gmii_phy_if.v")
-srcs.append("../lib/eth/rtl/eth_mac_1g_fifo.v")
+srcs.append("../lib/eth/rtl/eth_mac_1g_gmii_fifo.v")
+srcs.append("../lib/eth/rtl/eth_mac_1g_gmii.v")
 srcs.append("../lib/eth/rtl/eth_mac_1g.v")
-srcs.append("../lib/eth/rtl/eth_mac_1g_rx.v")
+srcs.append("../lib/eth/rtl/axis_gmii_rx.v")
-srcs.append("../lib/eth/rtl/eth_mac_1g_tx.v")
+srcs.append("../lib/eth/rtl/axis_gmii_tx.v")
 srcs.append("../lib/eth/rtl/lfsr.v")
 srcs.append("../lib/eth/rtl/eth_axis_rx.v")
 srcs.append("../lib/eth/rtl/eth_axis_tx.v")
@@ -96,6 +97,7 @@ def bench():
     phy_rxd = Signal(intbv(0)[8:])
     phy_rx_dv = Signal(bool(0))
     phy_rx_er = Signal(bool(0))
+    phy_tx_clk = Signal(bool(0))
     uart_rxd = Signal(bool(0))
 
     # Outputs
@@ -108,6 +110,8 @@ def bench():
     uart_txd = Signal(bool(0))
 
     # sources and sinks
+    mii_select = Signal(bool(0))
+
     gmii_source = gmii_ep.GMIISource()
 
     gmii_source_logic = gmii_source.create_logic(
@@ -116,6 +120,7 @@ def bench():
         txd=phy_rxd,
         tx_en=phy_rx_dv,
         tx_er=phy_rx_er,
+        mii_select=mii_select,
         name='gmii_source'
     )
 
@@ -127,6 +132,7 @@ def bench():
         rxd=phy_txd,
         rx_dv=phy_tx_en,
         rx_er=phy_tx_er,
+        mii_select=mii_select,
         name='gmii_sink'
     )
 
@@ -153,6 +159,7 @@ def bench():
         phy_rx_dv=phy_rx_dv,
         phy_rx_er=phy_rx_er,
         phy_gtx_clk=phy_gtx_clk,
+        phy_tx_clk=phy_tx_clk,
         phy_txd=phy_txd,
         phy_tx_en=phy_tx_en,
         phy_tx_er=phy_tx_er,
@@ -165,7 +172,15 @@ def bench():
     @always(delay(4))
     def clkgen():
         clk.next = not clk
+
+    rx_clk_hp = Signal(int(4))
+
+    @instance
+    def rx_clk_gen():
+        while True:
+            yield delay(int(rx_clk_hp))
             phy_rx_clk.next = not phy_rx_clk
+            phy_tx_clk.next = not phy_tx_clk
 
     @instance
     def check():
@@ -286,7 +301,7 @@ def bench():
 
         raise StopSimulation
 
-    return dut, gmii_source_logic, gmii_sink_logic, clkgen, check
+    return dut, gmii_source_logic, gmii_sink_logic, clkgen, rx_clk_gen, check
 
 def test_bench():
     sim = Simulation(bench())

example/ATLYS/fpga/tb/test_fpga_core.v

@@ -49,6 +49,7 @@ reg phy_rx_clk = 0;
 reg [7:0] phy_rxd = 0;
 reg phy_rx_dv = 0;
 reg phy_rx_er = 0;
+reg phy_tx_clk = 0;
 reg uart_rxd = 0;
 
 // Outputs
@@ -76,6 +77,7 @@ initial begin
         phy_rxd,
         phy_rx_dv,
         phy_rx_er,
+        phy_tx_clk,
         uart_rxd
     );
     $to_myhdl(
@@ -111,6 +113,7 @@ UUT (
     .phy_rx_dv(phy_rx_dv),
     .phy_rx_er(phy_rx_er),
     .phy_gtx_clk(phy_gtx_clk),
+    .phy_tx_clk(phy_tx_clk),
     .phy_txd(phy_txd),
     .phy_tx_en(phy_tx_en),
     .phy_tx_er(phy_tx_er),