FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Bitwise operators instead of generate

Browse Source
This commit is contained in:
Alex Forencich 2018-12-09 00:03:09 -08:00
parent 3d90e80da8
commit aa6991a4a5
1 changed files with 2 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
rtl/axis_arb_mux.v
View File

@ -123,14 +123,8 @@ arb_inst (
.grant_encoded(grant_encoded) .grant_encoded(grant_encoded)
); );
generate assign request = s_axis_tvalid & ~grant;
genvar n; assign acknowledge = grant & s_axis_tvalid & s_axis_tready & s_axis_tlast;
for (n = 0; n < S_COUNT; n = n + 1) begin
assign request[n] = s_axis_tvalid[n] && !grant[n];
assign acknowledge[n] = grant[n] && s_axis_tvalid[n] && s_axis_tready[n] && s_axis_tlast[n];
end
endgenerate
always @* begin always @* begin
// pass through selected packet data // pass through selected packet data