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Trim trailing spaces
This commit is contained in:
Alex Forencich
parent
3816eb3c20
commit
aafacb372e
@ -1,7 +1,7 @@
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#!/usr/bin/env python
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"""axis_crosspoint
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Generates an AXI Stream crosspoint switch with a specific number of ports
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Generates an AXI Stream crosspoint switch with the specified number of ports
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Usage: axis_crosspoint [OPTION]...
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-?, --help display this help and exit
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@ -106,29 +106,29 @@ module {{name}} #
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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{%- for p in ports %}
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{%- for p in ports %}
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input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
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input wire input_{{p}}_axis_tvalid,
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input wire input_{{p}}_axis_tlast,
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{% endfor %}
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{% endfor %}
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/*
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* AXI Stream outputs
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*/
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{%- for p in ports %}
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{%- for p in ports %}
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output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
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output wire output_{{p}}_axis_tvalid,
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output wire output_{{p}}_axis_tlast,
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{% endfor %}
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{% endfor %}
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/*
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* Control
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*/
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{%- for p in ports %}
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{%- for p in ports %}
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input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %}
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{%- endfor %}
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{%- endfor %}
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);
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{% for p in ports %}
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reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0;
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@ -153,38 +153,38 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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{%- for p in ports %}
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{%- for p in ports %}
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output_{{p}}_select_reg <= 0;
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{%- endfor %}
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{% for p in ports %}
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{%- endfor %}
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{% for p in ports %}
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input_{{p}}_axis_tvalid_reg <= 0;
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input_{{p}}_axis_tlast_reg <= 0;
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{%- endfor %}
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{% for p in ports %}
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{%- endfor %}
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{% for p in ports %}
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output_{{p}}_axis_tvalid_reg <= 0;
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output_{{p}}_axis_tlast_reg <= 0;
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{%- endfor %}
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{%- endfor %}
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end else begin
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{%- for p in ports %}
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{%- for p in ports %}
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input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
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input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
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input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
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{% endfor %}
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{%- for p in ports %}
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{% endfor %}
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{%- for p in ports %}
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output_{{p}}_select_reg <= output_{{p}}_select;
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{%- endfor %}
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{%- for p in ports %}
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{%- endfor %}
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{%- for p in ports %}
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case (output_{{p}}_select_reg)
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{%- for q in ports %}
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{%- for q in ports %}
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{{w}}'d{{q}}: begin
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output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
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output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
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output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
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end
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{%- endfor %}
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{%- endfor %}
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endcase
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{%- endfor %}
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{%- endfor %}
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end
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end
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@ -36,45 +36,45 @@ module axis_crosspoint_4x4 #
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
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input wire input_0_axis_tvalid,
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input wire input_0_axis_tlast,
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input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
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input wire input_1_axis_tvalid,
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input wire input_1_axis_tlast,
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input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
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input wire input_2_axis_tvalid,
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input wire input_2_axis_tlast,
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input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
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input wire input_3_axis_tvalid,
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input wire input_3_axis_tlast,
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/*
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* AXI Stream outputs
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*/
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output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
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output wire output_0_axis_tvalid,
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output wire output_0_axis_tlast,
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output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
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output wire output_1_axis_tvalid,
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output wire output_1_axis_tlast,
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output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
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output wire output_2_axis_tvalid,
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output wire output_2_axis_tlast,
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output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
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output wire output_3_axis_tvalid,
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output wire output_3_axis_tlast,
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/*
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* Control
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*/
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@ -144,7 +144,7 @@ always @(posedge clk or posedge rst) begin
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output_1_select_reg <= 0;
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output_2_select_reg <= 0;
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output_3_select_reg <= 0;
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input_0_axis_tvalid_reg <= 0;
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input_0_axis_tlast_reg <= 0;
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input_1_axis_tvalid_reg <= 0;
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@ -153,7 +153,7 @@ always @(posedge clk or posedge rst) begin
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input_2_axis_tlast_reg <= 0;
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input_3_axis_tvalid_reg <= 0;
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input_3_axis_tlast_reg <= 0;
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output_0_axis_tvalid_reg <= 0;
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output_0_axis_tlast_reg <= 0;
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output_1_axis_tvalid_reg <= 0;
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@ -166,24 +166,24 @@ always @(posedge clk or posedge rst) begin
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input_0_axis_tdata_reg <= input_0_axis_tdata;
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input_0_axis_tvalid_reg <= input_0_axis_tvalid;
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input_0_axis_tlast_reg <= input_0_axis_tlast;
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input_1_axis_tdata_reg <= input_1_axis_tdata;
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input_1_axis_tvalid_reg <= input_1_axis_tvalid;
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input_1_axis_tlast_reg <= input_1_axis_tlast;
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input_2_axis_tdata_reg <= input_2_axis_tdata;
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input_2_axis_tvalid_reg <= input_2_axis_tvalid;
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input_2_axis_tlast_reg <= input_2_axis_tlast;
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input_3_axis_tdata_reg <= input_3_axis_tdata;
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input_3_axis_tvalid_reg <= input_3_axis_tvalid;
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input_3_axis_tlast_reg <= input_3_axis_tlast;
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output_0_select_reg <= output_0_select;
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output_1_select_reg <= output_1_select;
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output_2_select_reg <= output_2_select;
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output_3_select_reg <= output_3_select;
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case (output_0_select_reg)
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2'd0: begin
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output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
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@ -206,7 +206,7 @@ always @(posedge clk or posedge rst) begin
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output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
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end
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endcase
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case (output_1_select_reg)
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2'd0: begin
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output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
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@ -229,7 +229,7 @@ always @(posedge clk or posedge rst) begin
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output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
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end
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endcase
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case (output_2_select_reg)
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2'd0: begin
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output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
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@ -252,7 +252,7 @@ always @(posedge clk or posedge rst) begin
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output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
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end
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endcase
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case (output_3_select_reg)
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2'd0: begin
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output_3_axis_tdata_reg <= input_0_axis_tdata_reg;
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@ -1,7 +1,7 @@
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#!/usr/bin/env python
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"""axis_crosspoint_64_64
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Generates an AXI Stream crosspoint switch with a specific number of ports
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Generates an AXI Stream crosspoint switch with the specified number of ports
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Usage: axis_crosspoint_64 [OPTION]...
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-?, --help display this help and exit
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@ -107,31 +107,31 @@ module {{name}} #
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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{%- for p in ports %}
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{%- for p in ports %}
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input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
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input wire input_{{p}}_axis_tvalid,
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input wire input_{{p}}_axis_tlast,
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{% endfor %}
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{% endfor %}
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/*
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* AXI Stream outputs
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*/
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{%- for p in ports %}
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{%- for p in ports %}
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output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
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output wire output_{{p}}_axis_tvalid,
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output wire output_{{p}}_axis_tlast,
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{% endfor %}
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{% endfor %}
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/*
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* Control
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*/
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{%- for p in ports %}
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{%- for p in ports %}
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input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %}
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{%- endfor %}
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{%- endfor %}
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);
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{% for p in ports %}
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reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0;
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@ -159,40 +159,40 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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{%- for p in ports %}
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{%- for p in ports %}
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output_{{p}}_select_reg <= 0;
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{%- endfor %}
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{% for p in ports %}
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{%- endfor %}
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{% for p in ports %}
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input_{{p}}_axis_tvalid_reg <= 0;
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input_{{p}}_axis_tlast_reg <= 0;
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{%- endfor %}
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{% for p in ports %}
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{%- endfor %}
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{% for p in ports %}
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output_{{p}}_axis_tvalid_reg <= 0;
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output_{{p}}_axis_tlast_reg <= 0;
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{%- endfor %}
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{%- endfor %}
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end else begin
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{%- for p in ports %}
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{%- for p in ports %}
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input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
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input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep;
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input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
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input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
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{% endfor %}
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{%- for p in ports %}
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{% endfor %}
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{%- for p in ports %}
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output_{{p}}_select_reg <= output_{{p}}_select;
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{%- endfor %}
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{%- for p in ports %}
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{%- endfor %}
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{%- for p in ports %}
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case (output_{{p}}_select_reg)
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{%- for q in ports %}
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{%- for q in ports %}
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{{w}}'d{{q}}: begin
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output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
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output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg;
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output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
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output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
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end
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{%- endfor %}
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{%- endfor %}
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endcase
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{%- endfor %}
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{%- endfor %}
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end
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end
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@ -37,7 +37,7 @@ module axis_crosspoint_64_4x4 #
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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@ -45,22 +45,22 @@ module axis_crosspoint_64_4x4 #
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input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
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input wire input_0_axis_tvalid,
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input wire input_0_axis_tlast,
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input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
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input wire input_1_axis_tvalid,
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input wire input_1_axis_tlast,
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input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
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input wire input_2_axis_tvalid,
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input wire input_2_axis_tlast,
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input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
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input wire input_3_axis_tvalid,
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input wire input_3_axis_tlast,
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/*
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* AXI Stream outputs
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*/
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@ -68,22 +68,22 @@ module axis_crosspoint_64_4x4 #
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output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
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output wire output_0_axis_tvalid,
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output wire output_0_axis_tlast,
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output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
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output wire output_1_axis_tvalid,
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output wire output_1_axis_tlast,
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output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
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output wire output_2_axis_tvalid,
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output wire output_2_axis_tlast,
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output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
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output wire output_3_axis_tvalid,
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output wire output_3_axis_tlast,
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/*
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* Control
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*/
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@ -165,7 +165,7 @@ always @(posedge clk or posedge rst) begin
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output_1_select_reg <= 0;
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output_2_select_reg <= 0;
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output_3_select_reg <= 0;
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input_0_axis_tvalid_reg <= 0;
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input_0_axis_tlast_reg <= 0;
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input_1_axis_tvalid_reg <= 0;
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@ -174,7 +174,7 @@ always @(posedge clk or posedge rst) begin
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input_2_axis_tlast_reg <= 0;
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input_3_axis_tvalid_reg <= 0;
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input_3_axis_tlast_reg <= 0;
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output_0_axis_tvalid_reg <= 0;
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output_0_axis_tlast_reg <= 0;
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output_1_axis_tvalid_reg <= 0;
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@ -188,27 +188,27 @@ always @(posedge clk or posedge rst) begin
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input_0_axis_tkeep_reg <= input_0_axis_tkeep;
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input_0_axis_tvalid_reg <= input_0_axis_tvalid;
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input_0_axis_tlast_reg <= input_0_axis_tlast;
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input_1_axis_tdata_reg <= input_1_axis_tdata;
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input_1_axis_tkeep_reg <= input_1_axis_tkeep;
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input_1_axis_tvalid_reg <= input_1_axis_tvalid;
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input_1_axis_tlast_reg <= input_1_axis_tlast;
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input_2_axis_tdata_reg <= input_2_axis_tdata;
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input_2_axis_tkeep_reg <= input_2_axis_tkeep;
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input_2_axis_tvalid_reg <= input_2_axis_tvalid;
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input_2_axis_tlast_reg <= input_2_axis_tlast;
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input_3_axis_tdata_reg <= input_3_axis_tdata;
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input_3_axis_tkeep_reg <= input_3_axis_tkeep;
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input_3_axis_tvalid_reg <= input_3_axis_tvalid;
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input_3_axis_tlast_reg <= input_3_axis_tlast;
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output_0_select_reg <= output_0_select;
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output_1_select_reg <= output_1_select;
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output_2_select_reg <= output_2_select;
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output_3_select_reg <= output_3_select;
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case (output_0_select_reg)
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2'd0: begin
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output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
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@ -235,7 +235,7 @@ always @(posedge clk or posedge rst) begin
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output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
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end
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endcase
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case (output_1_select_reg)
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2'd0: begin
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output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
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@ -262,7 +262,7 @@ always @(posedge clk or posedge rst) begin
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output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
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end
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endcase
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|
||||
|
||||
case (output_2_select_reg)
|
||||
2'd0: begin
|
||||
output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
|
||||
@ -289,7 +289,7 @@ always @(posedge clk or posedge rst) begin
|
||||
output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
|
||||
end
|
||||
endcase
|
||||
|
||||
|
||||
case (output_3_select_reg)
|
||||
2'd0: begin
|
||||
output_3_axis_tdata_reg <= input_0_axis_tdata_reg;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user