diff --git a/rtl/axis_crosspoint.py b/rtl/axis_crosspoint.py index dc8f2414..e779ad08 100755 --- a/rtl/axis_crosspoint.py +++ b/rtl/axis_crosspoint.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """axis_crosspoint -Generates an AXI Stream crosspoint switch with a specific number of ports +Generates an AXI Stream crosspoint switch with the specified number of ports Usage: axis_crosspoint [OPTION]... -?, --help display this help and exit @@ -106,29 +106,29 @@ module {{name}} # ( input wire clk, input wire rst, - + /* * AXI Stream inputs */ - {%- for p in ports %} +{%- for p in ports %} input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tlast, - {% endfor %} +{% endfor %} /* * AXI Stream outputs */ - {%- for p in ports %} +{%- for p in ports %} output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tlast, - {% endfor %} +{% endfor %} /* * Control */ - {%- for p in ports %} +{%- for p in ports %} input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %} - {%- endfor %} +{%- endfor %} ); {% for p in ports %} reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0; @@ -153,38 +153,38 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg; always @(posedge clk or posedge rst) begin if (rst) begin - {%- for p in ports %} +{%- for p in ports %} output_{{p}}_select_reg <= 0; - {%- endfor %} - {% for p in ports %} +{%- endfor %} +{% for p in ports %} input_{{p}}_axis_tvalid_reg <= 0; input_{{p}}_axis_tlast_reg <= 0; - {%- endfor %} - {% for p in ports %} +{%- endfor %} +{% for p in ports %} output_{{p}}_axis_tvalid_reg <= 0; output_{{p}}_axis_tlast_reg <= 0; - {%- endfor %} +{%- endfor %} end else begin - {%- for p in ports %} +{%- for p in ports %} input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata; input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid; input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast; - {% endfor %} - {%- for p in ports %} +{% endfor %} +{%- for p in ports %} output_{{p}}_select_reg <= output_{{p}}_select; - {%- endfor %} - {%- for p in ports %} - +{%- endfor %} +{%- for p in ports %} + case (output_{{p}}_select_reg) - {%- for q in ports %} +{%- for q in ports %} {{w}}'d{{q}}: begin output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg; output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg; output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg; end - {%- endfor %} +{%- endfor %} endcase - {%- endfor %} +{%- endfor %} end end diff --git a/rtl/axis_crosspoint_4x4.v b/rtl/axis_crosspoint_4x4.v index 1734f49f..859f4309 100644 --- a/rtl/axis_crosspoint_4x4.v +++ b/rtl/axis_crosspoint_4x4.v @@ -36,45 +36,45 @@ module axis_crosspoint_4x4 # ( input wire clk, input wire rst, - + /* * AXI Stream inputs */ input wire [DATA_WIDTH-1:0] input_0_axis_tdata, input wire input_0_axis_tvalid, input wire input_0_axis_tlast, - + input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire input_1_axis_tvalid, input wire input_1_axis_tlast, - + input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire input_2_axis_tvalid, input wire input_2_axis_tlast, - + input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire input_3_axis_tvalid, input wire input_3_axis_tlast, - + /* * AXI Stream outputs */ output wire [DATA_WIDTH-1:0] output_0_axis_tdata, output wire output_0_axis_tvalid, output wire output_0_axis_tlast, - + output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire output_1_axis_tvalid, output wire output_1_axis_tlast, - + output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire output_2_axis_tvalid, output wire output_2_axis_tlast, - + output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire output_3_axis_tvalid, output wire output_3_axis_tlast, - + /* * Control */ @@ -144,7 +144,7 @@ always @(posedge clk or posedge rst) begin output_1_select_reg <= 0; output_2_select_reg <= 0; output_3_select_reg <= 0; - + input_0_axis_tvalid_reg <= 0; input_0_axis_tlast_reg <= 0; input_1_axis_tvalid_reg <= 0; @@ -153,7 +153,7 @@ always @(posedge clk or posedge rst) begin input_2_axis_tlast_reg <= 0; input_3_axis_tvalid_reg <= 0; input_3_axis_tlast_reg <= 0; - + output_0_axis_tvalid_reg <= 0; output_0_axis_tlast_reg <= 0; output_1_axis_tvalid_reg <= 0; @@ -166,24 +166,24 @@ always @(posedge clk or posedge rst) begin input_0_axis_tdata_reg <= input_0_axis_tdata; input_0_axis_tvalid_reg <= input_0_axis_tvalid; input_0_axis_tlast_reg <= input_0_axis_tlast; - + input_1_axis_tdata_reg <= input_1_axis_tdata; input_1_axis_tvalid_reg <= input_1_axis_tvalid; input_1_axis_tlast_reg <= input_1_axis_tlast; - + input_2_axis_tdata_reg <= input_2_axis_tdata; input_2_axis_tvalid_reg <= input_2_axis_tvalid; input_2_axis_tlast_reg <= input_2_axis_tlast; - + input_3_axis_tdata_reg <= input_3_axis_tdata; input_3_axis_tvalid_reg <= input_3_axis_tvalid; input_3_axis_tlast_reg <= input_3_axis_tlast; - + output_0_select_reg <= output_0_select; output_1_select_reg <= output_1_select; output_2_select_reg <= output_2_select; output_3_select_reg <= output_3_select; - + case (output_0_select_reg) 2'd0: begin output_0_axis_tdata_reg <= input_0_axis_tdata_reg; @@ -206,7 +206,7 @@ always @(posedge clk or posedge rst) begin output_0_axis_tlast_reg <= input_3_axis_tlast_reg; end endcase - + case (output_1_select_reg) 2'd0: begin output_1_axis_tdata_reg <= input_0_axis_tdata_reg; @@ -229,7 +229,7 @@ always @(posedge clk or posedge rst) begin output_1_axis_tlast_reg <= input_3_axis_tlast_reg; end endcase - + case (output_2_select_reg) 2'd0: begin output_2_axis_tdata_reg <= input_0_axis_tdata_reg; @@ -252,7 +252,7 @@ always @(posedge clk or posedge rst) begin output_2_axis_tlast_reg <= input_3_axis_tlast_reg; end endcase - + case (output_3_select_reg) 2'd0: begin output_3_axis_tdata_reg <= input_0_axis_tdata_reg; diff --git a/rtl/axis_crosspoint_64.py b/rtl/axis_crosspoint_64.py index dea44e2e..fa674ffa 100755 --- a/rtl/axis_crosspoint_64.py +++ b/rtl/axis_crosspoint_64.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """axis_crosspoint_64_64 -Generates an AXI Stream crosspoint switch with a specific number of ports +Generates an AXI Stream crosspoint switch with the specified number of ports Usage: axis_crosspoint_64 [OPTION]... -?, --help display this help and exit @@ -107,31 +107,31 @@ module {{name}} # ( input wire clk, input wire rst, - + /* * AXI Stream inputs */ - {%- for p in ports %} +{%- for p in ports %} input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep, input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tlast, - {% endfor %} +{% endfor %} /* * AXI Stream outputs */ - {%- for p in ports %} +{%- for p in ports %} output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep, output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tlast, - {% endfor %} +{% endfor %} /* * Control */ - {%- for p in ports %} +{%- for p in ports %} input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %} - {%- endfor %} +{%- endfor %} ); {% for p in ports %} reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0; @@ -159,40 +159,40 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg; always @(posedge clk or posedge rst) begin if (rst) begin - {%- for p in ports %} +{%- for p in ports %} output_{{p}}_select_reg <= 0; - {%- endfor %} - {% for p in ports %} +{%- endfor %} +{% for p in ports %} input_{{p}}_axis_tvalid_reg <= 0; input_{{p}}_axis_tlast_reg <= 0; - {%- endfor %} - {% for p in ports %} +{%- endfor %} +{% for p in ports %} output_{{p}}_axis_tvalid_reg <= 0; output_{{p}}_axis_tlast_reg <= 0; - {%- endfor %} +{%- endfor %} end else begin - {%- for p in ports %} +{%- for p in ports %} input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata; input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep; input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid; input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast; - {% endfor %} - {%- for p in ports %} +{% endfor %} +{%- for p in ports %} output_{{p}}_select_reg <= output_{{p}}_select; - {%- endfor %} - {%- for p in ports %} - +{%- endfor %} +{%- for p in ports %} + case (output_{{p}}_select_reg) - {%- for q in ports %} +{%- for q in ports %} {{w}}'d{{q}}: begin output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg; output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg; output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg; output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg; end - {%- endfor %} +{%- endfor %} endcase - {%- endfor %} +{%- endfor %} end end diff --git a/rtl/axis_crosspoint_64_4x4.v b/rtl/axis_crosspoint_64_4x4.v index 25345c15..08c41ad5 100644 --- a/rtl/axis_crosspoint_64_4x4.v +++ b/rtl/axis_crosspoint_64_4x4.v @@ -37,7 +37,7 @@ module axis_crosspoint_64_4x4 # ( input wire clk, input wire rst, - + /* * AXI Stream inputs */ @@ -45,22 +45,22 @@ module axis_crosspoint_64_4x4 # input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep, input wire input_0_axis_tvalid, input wire input_0_axis_tlast, - + input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep, input wire input_1_axis_tvalid, input wire input_1_axis_tlast, - + input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep, input wire input_2_axis_tvalid, input wire input_2_axis_tlast, - + input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep, input wire input_3_axis_tvalid, input wire input_3_axis_tlast, - + /* * AXI Stream outputs */ @@ -68,22 +68,22 @@ module axis_crosspoint_64_4x4 # output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep, output wire output_0_axis_tvalid, output wire output_0_axis_tlast, - + output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep, output wire output_1_axis_tvalid, output wire output_1_axis_tlast, - + output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep, output wire output_2_axis_tvalid, output wire output_2_axis_tlast, - + output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep, output wire output_3_axis_tvalid, output wire output_3_axis_tlast, - + /* * Control */ @@ -165,7 +165,7 @@ always @(posedge clk or posedge rst) begin output_1_select_reg <= 0; output_2_select_reg <= 0; output_3_select_reg <= 0; - + input_0_axis_tvalid_reg <= 0; input_0_axis_tlast_reg <= 0; input_1_axis_tvalid_reg <= 0; @@ -174,7 +174,7 @@ always @(posedge clk or posedge rst) begin input_2_axis_tlast_reg <= 0; input_3_axis_tvalid_reg <= 0; input_3_axis_tlast_reg <= 0; - + output_0_axis_tvalid_reg <= 0; output_0_axis_tlast_reg <= 0; output_1_axis_tvalid_reg <= 0; @@ -188,27 +188,27 @@ always @(posedge clk or posedge rst) begin input_0_axis_tkeep_reg <= input_0_axis_tkeep; input_0_axis_tvalid_reg <= input_0_axis_tvalid; input_0_axis_tlast_reg <= input_0_axis_tlast; - + input_1_axis_tdata_reg <= input_1_axis_tdata; input_1_axis_tkeep_reg <= input_1_axis_tkeep; input_1_axis_tvalid_reg <= input_1_axis_tvalid; input_1_axis_tlast_reg <= input_1_axis_tlast; - + input_2_axis_tdata_reg <= input_2_axis_tdata; input_2_axis_tkeep_reg <= input_2_axis_tkeep; input_2_axis_tvalid_reg <= input_2_axis_tvalid; input_2_axis_tlast_reg <= input_2_axis_tlast; - + input_3_axis_tdata_reg <= input_3_axis_tdata; input_3_axis_tkeep_reg <= input_3_axis_tkeep; input_3_axis_tvalid_reg <= input_3_axis_tvalid; input_3_axis_tlast_reg <= input_3_axis_tlast; - + output_0_select_reg <= output_0_select; output_1_select_reg <= output_1_select; output_2_select_reg <= output_2_select; output_3_select_reg <= output_3_select; - + case (output_0_select_reg) 2'd0: begin output_0_axis_tdata_reg <= input_0_axis_tdata_reg; @@ -235,7 +235,7 @@ always @(posedge clk or posedge rst) begin output_0_axis_tlast_reg <= input_3_axis_tlast_reg; end endcase - + case (output_1_select_reg) 2'd0: begin output_1_axis_tdata_reg <= input_0_axis_tdata_reg; @@ -262,7 +262,7 @@ always @(posedge clk or posedge rst) begin output_1_axis_tlast_reg <= input_3_axis_tlast_reg; end endcase - + case (output_2_select_reg) 2'd0: begin output_2_axis_tdata_reg <= input_0_axis_tdata_reg; @@ -289,7 +289,7 @@ always @(posedge clk or posedge rst) begin output_2_axis_tlast_reg <= input_3_axis_tlast_reg; end endcase - + case (output_3_select_reg) 2'd0: begin output_3_axis_tdata_reg <= input_0_axis_tdata_reg;