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Alex Forencich 2014-11-12 15:32:05 -08:00
parent 3816eb3c20
commit aafacb372e
4 changed files with 84 additions and 84 deletions
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46
rtl/axis_crosspoint.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python #!/usr/bin/env python
"""axis_crosspoint """axis_crosspoint
Generates an AXI Stream crosspoint switch with a specific number of ports Generates an AXI Stream crosspoint switch with the specified number of ports
Usage: axis_crosspoint [OPTION]... Usage: axis_crosspoint [OPTION]...
-?, --help display this help and exit -?, --help display this help and exit
@ -106,29 +106,29 @@ module {{name}} #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI Stream inputs * AXI Stream inputs
*/ */
{%- for p in ports %} {%- for p in ports %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tvalid,
input wire input_{{p}}_axis_tlast, input wire input_{{p}}_axis_tlast,
{% endfor %} {% endfor %}
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
{%- for p in ports %} {%- for p in ports %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tvalid,
output wire output_{{p}}_axis_tlast, output wire output_{{p}}_axis_tlast,
{% endfor %} {% endfor %}
/* /*
* Control * Control
*/ */
{%- for p in ports %} {%- for p in ports %}
input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %} input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %}
{%- endfor %} {%- endfor %}
); );
{% for p in ports %} {% for p in ports %}
reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0; reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0;
@ -153,38 +153,38 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
always @(posedge clk or posedge rst) begin always @(posedge clk or posedge rst) begin
if (rst) begin if (rst) begin
{%- for p in ports %} {%- for p in ports %}
output_{{p}}_select_reg <= 0; output_{{p}}_select_reg <= 0;
{%- endfor %} {%- endfor %}
{% for p in ports %} {% for p in ports %}
input_{{p}}_axis_tvalid_reg <= 0; input_{{p}}_axis_tvalid_reg <= 0;
input_{{p}}_axis_tlast_reg <= 0; input_{{p}}_axis_tlast_reg <= 0;
{%- endfor %} {%- endfor %}
{% for p in ports %} {% for p in ports %}
output_{{p}}_axis_tvalid_reg <= 0; output_{{p}}_axis_tvalid_reg <= 0;
output_{{p}}_axis_tlast_reg <= 0; output_{{p}}_axis_tlast_reg <= 0;
{%- endfor %} {%- endfor %}
end else begin end else begin
{%- for p in ports %} {%- for p in ports %}
input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata; input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid; input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast; input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
{% endfor %} {% endfor %}
{%- for p in ports %} {%- for p in ports %}
output_{{p}}_select_reg <= output_{{p}}_select; output_{{p}}_select_reg <= output_{{p}}_select;
{%- endfor %} {%- endfor %}
{%- for p in ports %} {%- for p in ports %}
case (output_{{p}}_select_reg) case (output_{{p}}_select_reg)
{%- for q in ports %} {%- for q in ports %}
{{w}}'d{{q}}: begin {{w}}'d{{q}}: begin
output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg; output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg; output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg; output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
end end
{%- endfor %} {%- endfor %}
endcase endcase
{%- endfor %} {%- endfor %}
end end
end end

38
rtl/axis_crosspoint_4x4.v
View File

@ -36,45 +36,45 @@ module axis_crosspoint_4x4 #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI Stream inputs * AXI Stream inputs
*/ */
input wire [DATA_WIDTH-1:0] input_0_axis_tdata, input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire input_0_axis_tvalid, input wire input_0_axis_tvalid,
input wire input_0_axis_tlast, input wire input_0_axis_tlast,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire input_1_axis_tvalid, input wire input_1_axis_tvalid,
input wire input_1_axis_tlast, input wire input_1_axis_tlast,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire input_2_axis_tvalid, input wire input_2_axis_tvalid,
input wire input_2_axis_tlast, input wire input_2_axis_tlast,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire input_3_axis_tvalid, input wire input_3_axis_tvalid,
input wire input_3_axis_tlast, input wire input_3_axis_tlast,
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
output wire [DATA_WIDTH-1:0] output_0_axis_tdata, output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire output_0_axis_tvalid, output wire output_0_axis_tvalid,
output wire output_0_axis_tlast, output wire output_0_axis_tlast,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire output_1_axis_tvalid, output wire output_1_axis_tvalid,
output wire output_1_axis_tlast, output wire output_1_axis_tlast,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire output_2_axis_tvalid, output wire output_2_axis_tvalid,
output wire output_2_axis_tlast, output wire output_2_axis_tlast,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire output_3_axis_tvalid, output wire output_3_axis_tvalid,
output wire output_3_axis_tlast, output wire output_3_axis_tlast,
/* /*
* Control * Control
*/ */
@ -144,7 +144,7 @@ always @(posedge clk or posedge rst) begin
output_1_select_reg <= 0; output_1_select_reg <= 0;
output_2_select_reg <= 0; output_2_select_reg <= 0;
output_3_select_reg <= 0; output_3_select_reg <= 0;
input_0_axis_tvalid_reg <= 0; input_0_axis_tvalid_reg <= 0;
input_0_axis_tlast_reg <= 0; input_0_axis_tlast_reg <= 0;
input_1_axis_tvalid_reg <= 0; input_1_axis_tvalid_reg <= 0;
@ -153,7 +153,7 @@ always @(posedge clk or posedge rst) begin
input_2_axis_tlast_reg <= 0; input_2_axis_tlast_reg <= 0;
input_3_axis_tvalid_reg <= 0; input_3_axis_tvalid_reg <= 0;
input_3_axis_tlast_reg <= 0; input_3_axis_tlast_reg <= 0;
output_0_axis_tvalid_reg <= 0; output_0_axis_tvalid_reg <= 0;
output_0_axis_tlast_reg <= 0; output_0_axis_tlast_reg <= 0;
output_1_axis_tvalid_reg <= 0; output_1_axis_tvalid_reg <= 0;
@ -166,24 +166,24 @@ always @(posedge clk or posedge rst) begin
input_0_axis_tdata_reg <= input_0_axis_tdata; input_0_axis_tdata_reg <= input_0_axis_tdata;
input_0_axis_tvalid_reg <= input_0_axis_tvalid; input_0_axis_tvalid_reg <= input_0_axis_tvalid;
input_0_axis_tlast_reg <= input_0_axis_tlast; input_0_axis_tlast_reg <= input_0_axis_tlast;
input_1_axis_tdata_reg <= input_1_axis_tdata; input_1_axis_tdata_reg <= input_1_axis_tdata;
input_1_axis_tvalid_reg <= input_1_axis_tvalid; input_1_axis_tvalid_reg <= input_1_axis_tvalid;
input_1_axis_tlast_reg <= input_1_axis_tlast; input_1_axis_tlast_reg <= input_1_axis_tlast;
input_2_axis_tdata_reg <= input_2_axis_tdata; input_2_axis_tdata_reg <= input_2_axis_tdata;
input_2_axis_tvalid_reg <= input_2_axis_tvalid; input_2_axis_tvalid_reg <= input_2_axis_tvalid;
input_2_axis_tlast_reg <= input_2_axis_tlast; input_2_axis_tlast_reg <= input_2_axis_tlast;
input_3_axis_tdata_reg <= input_3_axis_tdata; input_3_axis_tdata_reg <= input_3_axis_tdata;
input_3_axis_tvalid_reg <= input_3_axis_tvalid; input_3_axis_tvalid_reg <= input_3_axis_tvalid;
input_3_axis_tlast_reg <= input_3_axis_tlast; input_3_axis_tlast_reg <= input_3_axis_tlast;
output_0_select_reg <= output_0_select; output_0_select_reg <= output_0_select;
output_1_select_reg <= output_1_select; output_1_select_reg <= output_1_select;
output_2_select_reg <= output_2_select; output_2_select_reg <= output_2_select;
output_3_select_reg <= output_3_select; output_3_select_reg <= output_3_select;
case (output_0_select_reg) case (output_0_select_reg)
2'd0: begin 2'd0: begin
output_0_axis_tdata_reg <= input_0_axis_tdata_reg; output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
@ -206,7 +206,7 @@ always @(posedge clk or posedge rst) begin
output_0_axis_tlast_reg <= input_3_axis_tlast_reg; output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
end end
endcase endcase
case (output_1_select_reg) case (output_1_select_reg)
2'd0: begin 2'd0: begin
output_1_axis_tdata_reg <= input_0_axis_tdata_reg; output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
@ -229,7 +229,7 @@ always @(posedge clk or posedge rst) begin
output_1_axis_tlast_reg <= input_3_axis_tlast_reg; output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
end end
endcase endcase
case (output_2_select_reg) case (output_2_select_reg)
2'd0: begin 2'd0: begin
output_2_axis_tdata_reg <= input_0_axis_tdata_reg; output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
@ -252,7 +252,7 @@ always @(posedge clk or posedge rst) begin
output_2_axis_tlast_reg <= input_3_axis_tlast_reg; output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
end end
endcase endcase
case (output_3_select_reg) case (output_3_select_reg)
2'd0: begin 2'd0: begin
output_3_axis_tdata_reg <= input_0_axis_tdata_reg; output_3_axis_tdata_reg <= input_0_axis_tdata_reg;

46
rtl/axis_crosspoint_64.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python #!/usr/bin/env python
"""axis_crosspoint_64_64 """axis_crosspoint_64_64
Generates an AXI Stream crosspoint switch with a specific number of ports Generates an AXI Stream crosspoint switch with the specified number of ports
Usage: axis_crosspoint_64 [OPTION]... Usage: axis_crosspoint_64 [OPTION]...
-?, --help display this help and exit -?, --help display this help and exit
@ -107,31 +107,31 @@ module {{name}} #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI Stream inputs * AXI Stream inputs
*/ */
{%- for p in ports %} {%- for p in ports %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep, input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tvalid,
input wire input_{{p}}_axis_tlast, input wire input_{{p}}_axis_tlast,
{% endfor %} {% endfor %}
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
{%- for p in ports %} {%- for p in ports %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep, output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tvalid,
output wire output_{{p}}_axis_tlast, output wire output_{{p}}_axis_tlast,
{% endfor %} {% endfor %}
/* /*
* Control * Control
*/ */
{%- for p in ports %} {%- for p in ports %}
input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %} input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %}
{%- endfor %} {%- endfor %}
); );
{% for p in ports %} {% for p in ports %}
reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0; reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0;
@ -159,40 +159,40 @@ assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
always @(posedge clk or posedge rst) begin always @(posedge clk or posedge rst) begin
if (rst) begin if (rst) begin
{%- for p in ports %} {%- for p in ports %}
output_{{p}}_select_reg <= 0; output_{{p}}_select_reg <= 0;
{%- endfor %} {%- endfor %}
{% for p in ports %} {% for p in ports %}
input_{{p}}_axis_tvalid_reg <= 0; input_{{p}}_axis_tvalid_reg <= 0;
input_{{p}}_axis_tlast_reg <= 0; input_{{p}}_axis_tlast_reg <= 0;
{%- endfor %} {%- endfor %}
{% for p in ports %} {% for p in ports %}
output_{{p}}_axis_tvalid_reg <= 0; output_{{p}}_axis_tvalid_reg <= 0;
output_{{p}}_axis_tlast_reg <= 0; output_{{p}}_axis_tlast_reg <= 0;
{%- endfor %} {%- endfor %}
end else begin end else begin
{%- for p in ports %} {%- for p in ports %}
input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata; input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep; input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep;
input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid; input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast; input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
{% endfor %} {% endfor %}
{%- for p in ports %} {%- for p in ports %}
output_{{p}}_select_reg <= output_{{p}}_select; output_{{p}}_select_reg <= output_{{p}}_select;
{%- endfor %} {%- endfor %}
{%- for p in ports %} {%- for p in ports %}
case (output_{{p}}_select_reg) case (output_{{p}}_select_reg)
{%- for q in ports %} {%- for q in ports %}
{{w}}'d{{q}}: begin {{w}}'d{{q}}: begin
output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg; output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg; output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg;
output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg; output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg; output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
end end
{%- endfor %} {%- endfor %}
endcase endcase
{%- endfor %} {%- endfor %}
end end
end end

38
rtl/axis_crosspoint_64_4x4.v
View File

@ -37,7 +37,7 @@ module axis_crosspoint_64_4x4 #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI Stream inputs * AXI Stream inputs
*/ */
@ -45,22 +45,22 @@ module axis_crosspoint_64_4x4 #
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep, input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid, input wire input_0_axis_tvalid,
input wire input_0_axis_tlast, input wire input_0_axis_tlast,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep, input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid, input wire input_1_axis_tvalid,
input wire input_1_axis_tlast, input wire input_1_axis_tlast,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep, input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid, input wire input_2_axis_tvalid,
input wire input_2_axis_tlast, input wire input_2_axis_tlast,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep, input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid, input wire input_3_axis_tvalid,
input wire input_3_axis_tlast, input wire input_3_axis_tlast,
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
@ -68,22 +68,22 @@ module axis_crosspoint_64_4x4 #
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep, output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
output wire output_0_axis_tvalid, output wire output_0_axis_tvalid,
output wire output_0_axis_tlast, output wire output_0_axis_tlast,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep, output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
output wire output_1_axis_tvalid, output wire output_1_axis_tvalid,
output wire output_1_axis_tlast, output wire output_1_axis_tlast,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep, output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
output wire output_2_axis_tvalid, output wire output_2_axis_tvalid,
output wire output_2_axis_tlast, output wire output_2_axis_tlast,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep, output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
output wire output_3_axis_tvalid, output wire output_3_axis_tvalid,
output wire output_3_axis_tlast, output wire output_3_axis_tlast,
/* /*
* Control * Control
*/ */
@ -165,7 +165,7 @@ always @(posedge clk or posedge rst) begin
output_1_select_reg <= 0; output_1_select_reg <= 0;
output_2_select_reg <= 0; output_2_select_reg <= 0;
output_3_select_reg <= 0; output_3_select_reg <= 0;
input_0_axis_tvalid_reg <= 0; input_0_axis_tvalid_reg <= 0;
input_0_axis_tlast_reg <= 0; input_0_axis_tlast_reg <= 0;
input_1_axis_tvalid_reg <= 0; input_1_axis_tvalid_reg <= 0;
@ -174,7 +174,7 @@ always @(posedge clk or posedge rst) begin
input_2_axis_tlast_reg <= 0; input_2_axis_tlast_reg <= 0;
input_3_axis_tvalid_reg <= 0; input_3_axis_tvalid_reg <= 0;
input_3_axis_tlast_reg <= 0; input_3_axis_tlast_reg <= 0;
output_0_axis_tvalid_reg <= 0; output_0_axis_tvalid_reg <= 0;
output_0_axis_tlast_reg <= 0; output_0_axis_tlast_reg <= 0;
output_1_axis_tvalid_reg <= 0; output_1_axis_tvalid_reg <= 0;
@ -188,27 +188,27 @@ always @(posedge clk or posedge rst) begin
input_0_axis_tkeep_reg <= input_0_axis_tkeep; input_0_axis_tkeep_reg <= input_0_axis_tkeep;
input_0_axis_tvalid_reg <= input_0_axis_tvalid; input_0_axis_tvalid_reg <= input_0_axis_tvalid;
input_0_axis_tlast_reg <= input_0_axis_tlast; input_0_axis_tlast_reg <= input_0_axis_tlast;
input_1_axis_tdata_reg <= input_1_axis_tdata; input_1_axis_tdata_reg <= input_1_axis_tdata;
input_1_axis_tkeep_reg <= input_1_axis_tkeep; input_1_axis_tkeep_reg <= input_1_axis_tkeep;
input_1_axis_tvalid_reg <= input_1_axis_tvalid; input_1_axis_tvalid_reg <= input_1_axis_tvalid;
input_1_axis_tlast_reg <= input_1_axis_tlast; input_1_axis_tlast_reg <= input_1_axis_tlast;
input_2_axis_tdata_reg <= input_2_axis_tdata; input_2_axis_tdata_reg <= input_2_axis_tdata;
input_2_axis_tkeep_reg <= input_2_axis_tkeep; input_2_axis_tkeep_reg <= input_2_axis_tkeep;
input_2_axis_tvalid_reg <= input_2_axis_tvalid; input_2_axis_tvalid_reg <= input_2_axis_tvalid;
input_2_axis_tlast_reg <= input_2_axis_tlast; input_2_axis_tlast_reg <= input_2_axis_tlast;
input_3_axis_tdata_reg <= input_3_axis_tdata; input_3_axis_tdata_reg <= input_3_axis_tdata;
input_3_axis_tkeep_reg <= input_3_axis_tkeep; input_3_axis_tkeep_reg <= input_3_axis_tkeep;
input_3_axis_tvalid_reg <= input_3_axis_tvalid; input_3_axis_tvalid_reg <= input_3_axis_tvalid;
input_3_axis_tlast_reg <= input_3_axis_tlast; input_3_axis_tlast_reg <= input_3_axis_tlast;
output_0_select_reg <= output_0_select; output_0_select_reg <= output_0_select;
output_1_select_reg <= output_1_select; output_1_select_reg <= output_1_select;
output_2_select_reg <= output_2_select; output_2_select_reg <= output_2_select;
output_3_select_reg <= output_3_select; output_3_select_reg <= output_3_select;
case (output_0_select_reg) case (output_0_select_reg)
2'd0: begin 2'd0: begin
output_0_axis_tdata_reg <= input_0_axis_tdata_reg; output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
@ -235,7 +235,7 @@ always @(posedge clk or posedge rst) begin
output_0_axis_tlast_reg <= input_3_axis_tlast_reg; output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
end end
endcase endcase
case (output_1_select_reg) case (output_1_select_reg)
2'd0: begin 2'd0: begin
output_1_axis_tdata_reg <= input_0_axis_tdata_reg; output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
@ -262,7 +262,7 @@ always @(posedge clk or posedge rst) begin
output_1_axis_tlast_reg <= input_3_axis_tlast_reg; output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
end end
endcase endcase
case (output_2_select_reg) case (output_2_select_reg)
2'd0: begin 2'd0: begin
output_2_axis_tdata_reg <= input_0_axis_tdata_reg; output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
@ -289,7 +289,7 @@ always @(posedge clk or posedge rst) begin
output_2_axis_tlast_reg <= input_3_axis_tlast_reg; output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
end end
endcase endcase
case (output_3_select_reg) case (output_3_select_reg)
2'd0: begin 2'd0: begin
output_3_axis_tdata_reg <= input_0_axis_tdata_reg; output_3_axis_tdata_reg <= input_0_axis_tdata_reg;