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Properly reset all registers

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This commit is contained in:
Alex Forencich 2015-07-13 23:15:09 -07:00
parent dfab866e99
commit ac97cffc2b
4 changed files with 6 additions and 0 deletions
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2
rtl/axis_srl_fifo.v
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@ -115,6 +115,8 @@ end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
empty_reg <= 1;
end else begin
if (shift) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};

2
rtl/axis_srl_fifo_64.v
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@ -118,6 +118,8 @@ end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
empty_reg <= 1;
end else begin
if (shift) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};

1
rtl/axis_srl_register.v
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@ -77,6 +77,7 @@ end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;

1
rtl/axis_srl_register_64.v
View File

@ -80,6 +80,7 @@ end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;