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https://github.com/alexforencich/verilog-ethernet.git
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Fix initial values
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16e5ec2106
commit
adb9c4d147
@ -90,7 +90,7 @@ reg [TS_NS_WIDTH-1:0] ts_ns_reg = 0;
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reg [FNS_WIDTH-1:0] ts_fns_reg = 0;
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reg [TS_NS_WIDTH-1:0] ts_ns_inc_reg = 0;
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reg [FNS_WIDTH-1:0] ts_fns_inc_reg = 0;
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reg [TS_NS_WIDTH+1-1:0] ts_ns_ovf_reg = {TS_NS_WIDTH{1'b1}};
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reg [TS_NS_WIDTH+1-1:0] ts_ns_ovf_reg = {TS_NS_WIDTH+1{1'b1}};
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reg [FNS_WIDTH-1:0] ts_fns_ovf_reg = {FNS_WIDTH{1'b1}};
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reg ts_step_reg = 1'b0;
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@ -444,7 +444,7 @@ always @(posedge output_clk) begin
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ts_fns_reg <= 0;
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ts_ns_inc_reg <= 0;
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ts_fns_inc_reg <= 0;
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ts_ns_ovf_reg <= {TS_NS_WIDTH{1'b1}};
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ts_ns_ovf_reg <= {TS_NS_WIDTH+1{1'b1}};
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ts_fns_ovf_reg <= {FNS_WIDTH{1'b1}};
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ts_step_reg <= 0;
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pps_reg <= 0;
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