FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Update S10MX SDC

Browse Source
This commit is contained in:
Alex Forencich 2021-05-19 21:57:48 -07:00
parent 9df253aa59
commit b09e01ba48
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
example/S10MX_DK/fpga_10g/fpga.sdc
View File

@ -57,7 +57,7 @@ source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
# clocking infrastructure
constrain_sync_reset_inst "sync_reset_100mhz_inst"
# PHY RX clocks
# PHY clocks
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]