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Update async FIFO resets

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This commit is contained in:
Alex Forencich 2016-07-27 13:42:44 -07:00
parent c27e74c7d4
commit b44e401b95
4 changed files with 4 additions and 4 deletions
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2
rtl/axis_async_fifo.v
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@ -125,7 +125,7 @@ always @(posedge output_clk or posedge async_rst) begin
output_rst_sync3_reg <= 1'b1;
end else begin
output_rst_sync1_reg <= 1'b0;
output_rst_sync2_reg <= output_rst_sync1_reg;
output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
output_rst_sync3_reg <= output_rst_sync2_reg;
end
end

2
rtl/axis_async_fifo_64.v
View File

@ -128,7 +128,7 @@ always @(posedge output_clk or posedge async_rst) begin
output_rst_sync3_reg <= 1'b1;
end else begin
output_rst_sync1_reg <= 1'b0;
output_rst_sync2_reg <= output_rst_sync1_reg;
output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
output_rst_sync3_reg <= output_rst_sync2_reg;
end
end

2
rtl/axis_async_frame_fifo.v
View File

@ -165,7 +165,7 @@ always @(posedge output_clk or posedge async_rst) begin
output_rst_sync3_reg <= 1'b1;
end else begin
output_rst_sync1_reg <= 1'b0;
output_rst_sync2_reg <= output_rst_sync1_reg;
output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
output_rst_sync3_reg <= output_rst_sync2_reg;
end
end

2
rtl/axis_async_frame_fifo_64.v
View File

@ -168,7 +168,7 @@ always @(posedge output_clk or posedge async_rst) begin
output_rst_sync3_reg <= 1'b1;
end else begin
output_rst_sync1_reg <= 1'b0;
output_rst_sync2_reg <= output_rst_sync1_reg;
output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
output_rst_sync3_reg <= output_rst_sync2_reg;
end
end