From b44e401b95fe68909702d742c04d06f5ffdf46b7 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 27 Jul 2016 13:42:44 -0700
Subject: [PATCH] Update async FIFO resets

---
 rtl/axis_async_fifo.v          | 2 +-
 rtl/axis_async_fifo_64.v       | 2 +-
 rtl/axis_async_frame_fifo.v    | 2 +-
 rtl/axis_async_frame_fifo_64.v | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v
index f7542281..fc7af935 100644
--- a/rtl/axis_async_fifo.v
+++ b/rtl/axis_async_fifo.v
@@ -125,7 +125,7 @@ always @(posedge output_clk or posedge async_rst) begin
         output_rst_sync3_reg <= 1'b1;
     end else begin
         output_rst_sync1_reg <= 1'b0;
-        output_rst_sync2_reg <= output_rst_sync1_reg;
+        output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
         output_rst_sync3_reg <= output_rst_sync2_reg;
     end
 end
diff --git a/rtl/axis_async_fifo_64.v b/rtl/axis_async_fifo_64.v
index 510d38c4..135cee21 100644
--- a/rtl/axis_async_fifo_64.v
+++ b/rtl/axis_async_fifo_64.v
@@ -128,7 +128,7 @@ always @(posedge output_clk or posedge async_rst) begin
         output_rst_sync3_reg <= 1'b1;
     end else begin
         output_rst_sync1_reg <= 1'b0;
-        output_rst_sync2_reg <= output_rst_sync1_reg;
+        output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
         output_rst_sync3_reg <= output_rst_sync2_reg;
     end
 end
diff --git a/rtl/axis_async_frame_fifo.v b/rtl/axis_async_frame_fifo.v
index 98d1d87e..2469e3b3 100644
--- a/rtl/axis_async_frame_fifo.v
+++ b/rtl/axis_async_frame_fifo.v
@@ -165,7 +165,7 @@ always @(posedge output_clk or posedge async_rst) begin
         output_rst_sync3_reg <= 1'b1;
     end else begin
         output_rst_sync1_reg <= 1'b0;
-        output_rst_sync2_reg <= output_rst_sync1_reg;
+        output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
         output_rst_sync3_reg <= output_rst_sync2_reg;
     end
 end
diff --git a/rtl/axis_async_frame_fifo_64.v b/rtl/axis_async_frame_fifo_64.v
index 0e63c4ae..5399898c 100644
--- a/rtl/axis_async_frame_fifo_64.v
+++ b/rtl/axis_async_frame_fifo_64.v
@@ -168,7 +168,7 @@ always @(posedge output_clk or posedge async_rst) begin
         output_rst_sync3_reg <= 1'b1;
     end else begin
         output_rst_sync1_reg <= 1'b0;
-        output_rst_sync2_reg <= output_rst_sync1_reg;
+        output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
         output_rst_sync3_reg <= output_rst_sync2_reg;
     end
 end