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Code Issues Projects Releases Wiki Activity

AXI stream updates

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This commit is contained in:
Alex Forencich 2018-02-26 00:08:08 -08:00
parent 18787c2eed
commit bd27156f35
29 changed files with 272 additions and 40 deletions
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13
example/ATLYS/fpga/rtl/fpga_core.v
View File

@ -545,7 +545,12 @@ udp_complete_inst (
axis_fifo #(
.ADDR_WIDTH(12),
.DATA_WIDTH(8)
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk),
@ -553,16 +558,22 @@ udp_payload_fifo (
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

4
example/DE5-Net/fpga/fpga/Makefile
View File

@ -40,8 +40,8 @@ SYN_FILES += lib/eth/rtl/xgmii_interleave.v
SYN_FILES += lib/eth/rtl/xgmii_deinterleave.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += cores/phy/phy.qip
SYN_FILES += cores/phy_reconfig/phy_reconfig.qip

14
example/DE5-Net/fpga/rtl/fpga_core.v
View File

@ -564,9 +564,15 @@ udp_complete_inst (
.clear_arp_cache(1'b0)
);
axis_fifo_64 #(
axis_fifo #(
.ADDR_WIDTH(10),
.DATA_WIDTH(64)
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(64),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk),
@ -578,6 +584,8 @@ udp_payload_fifo (
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
@ -586,6 +594,8 @@ udp_payload_fifo (
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

4
example/DE5-Net/fpga/tb/test_fpga_core.py
View File

@ -63,8 +63,8 @@ srcs.append("../lib/eth/rtl/eth_arb_mux_64_2.v")
srcs.append("../lib/eth/rtl/eth_mux_64_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo_64.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo_64.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

4
example/HXT100G/fpga/fpga/Makefile
View File

@ -45,8 +45,8 @@ SYN_FILES += lib/eth/rtl/xgmii_interleave.v
SYN_FILES += lib/eth/rtl/xgmii_deinterleave.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v

14
example/HXT100G/fpga/rtl/fpga_core.v
View File

@ -708,9 +708,15 @@ udp_complete_inst (
.clear_arp_cache(1'b0)
);
axis_fifo_64 #(
axis_fifo #(
.ADDR_WIDTH(10),
.DATA_WIDTH(64)
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(64),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk),
@ -722,6 +728,8 @@ udp_payload_fifo (
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
@ -730,6 +738,8 @@ udp_payload_fifo (
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

4
example/HXT100G/fpga/tb/test_fpga_core.py
View File

@ -63,8 +63,8 @@ srcs.append("../lib/eth/rtl/eth_arb_mux_64_2.v")
srcs.append("../lib/eth/rtl/eth_mux_64_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo_64.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo_64.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

13
example/ML605/fpga_gmii/rtl/fpga_core.v
View File

@ -558,7 +558,12 @@ udp_complete_inst (
axis_fifo #(
.ADDR_WIDTH(12),
.DATA_WIDTH(8)
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk_125mhz),
@ -566,16 +571,22 @@ udp_payload_fifo (
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

13
example/ML605/fpga_rgmii/rtl/fpga_core.v
View File

@ -555,7 +555,12 @@ udp_complete_inst (
axis_fifo #(
.ADDR_WIDTH(12),
.DATA_WIDTH(8)
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk_125mhz),
@ -563,16 +568,22 @@ udp_payload_fifo (
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

13
example/ML605/fpga_sgmii/rtl/fpga_core.v
View File

@ -555,7 +555,12 @@ udp_complete_inst (
axis_fifo #(
.ADDR_WIDTH(12),
.DATA_WIDTH(8)
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk_125mhz),
@ -563,16 +568,22 @@ udp_payload_fifo (
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

13
example/NexysVideo/fpga/rtl/fpga_core.v
View File

@ -544,7 +544,12 @@ udp_complete_inst (
axis_fifo #(
.ADDR_WIDTH(12),
.DATA_WIDTH(8)
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk),
@ -552,16 +557,22 @@ udp_payload_fifo (
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

4
example/VCU108/fpga_10g/fpga/Makefile
View File

@ -44,10 +44,8 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch_64_4x4.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch_4x4.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo_64.v
# XDC files
XDC_FILES = fpga.xdc

27
example/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -562,10 +562,13 @@ always @* begin
end
end
axis_switch_64_4x4 #(
axis_switch_4x4 #(
.DATA_WIDTH(64),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_WIDTH(2),
.USER_ENABLE(1),
.USER_WIDTH(1),
.OUT_0_BASE(0),
.OUT_0_TOP(0),
.OUT_0_CONNECT(4'b1111),
@ -590,6 +593,7 @@ axis_switch_inst (
.input_0_axis_tvalid(mac_rx_axis_tvalid),
.input_0_axis_tready(mac_rx_axis_tready),
.input_0_axis_tlast(mac_rx_axis_tlast),
.input_0_axis_tid(0),
.input_0_axis_tdest(mac_rx_tdest),
.input_0_axis_tuser(mac_rx_axis_tuser),
.input_1_axis_tdata(tx_axis_tdata),
@ -597,6 +601,7 @@ axis_switch_inst (
.input_1_axis_tvalid(tx_axis_tvalid),
.input_1_axis_tready(tx_axis_tready),
.input_1_axis_tlast(tx_axis_tlast),
.input_1_axis_tid(0),
.input_1_axis_tdest(tx_tdest),
.input_1_axis_tuser(tx_axis_tuser),
.input_2_axis_tdata(gig_rx_axis_tdata_64),
@ -604,6 +609,7 @@ axis_switch_inst (
.input_2_axis_tvalid(gig_rx_axis_tvalid_64),
.input_2_axis_tready(gig_rx_axis_tready_64),
.input_2_axis_tlast(gig_rx_axis_tlast_64),
.input_2_axis_tid(0),
.input_2_axis_tdest(gig_rx_tdest),
.input_2_axis_tuser(gig_rx_axis_tuser_64),
.input_3_axis_tdata(64'd0),
@ -611,6 +617,7 @@ axis_switch_inst (
.input_3_axis_tvalid(1'b0),
.input_3_axis_tready(),
.input_3_axis_tlast(1'b0),
.input_3_axis_tid(0),
.input_3_axis_tdest(2'd0),
.input_3_axis_tuser(1'b0),
// AXI outputs
@ -619,6 +626,7 @@ axis_switch_inst (
.output_0_axis_tvalid(mac_tx_axis_tvalid),
.output_0_axis_tready(mac_tx_axis_tready),
.output_0_axis_tlast(mac_tx_axis_tlast),
.output_0_axis_tid(),
.output_0_axis_tdest(),
.output_0_axis_tuser(mac_tx_axis_tuser),
.output_1_axis_tdata(rx_axis_tdata),
@ -626,6 +634,7 @@ axis_switch_inst (
.output_1_axis_tvalid(rx_axis_tvalid),
.output_1_axis_tready(rx_axis_tready),
.output_1_axis_tlast(rx_axis_tlast),
.output_1_axis_tid(),
.output_1_axis_tdest(),
.output_1_axis_tuser(rx_axis_tuser),
.output_2_axis_tdata(gig_tx_axis_tdata_64),
@ -633,6 +642,7 @@ axis_switch_inst (
.output_2_axis_tvalid(gig_tx_axis_tvalid_64),
.output_2_axis_tready(gig_tx_axis_tready_64),
.output_2_axis_tlast(gig_tx_axis_tlast_64),
.output_2_axis_tid(),
.output_2_axis_tdest(),
.output_2_axis_tuser(gig_tx_axis_tuser_64),
.output_3_axis_tdata(),
@ -640,6 +650,7 @@ axis_switch_inst (
.output_3_axis_tvalid(),
.output_3_axis_tready(1'b1),
.output_3_axis_tlast(),
.output_3_axis_tid(),
.output_3_axis_tdest(),
.output_3_axis_tuser()
);
@ -837,9 +848,15 @@ udp_complete_inst (
.clear_arp_cache(1'b0)
);
axis_fifo_64 #(
axis_fifo #(
.ADDR_WIDTH(10),
.DATA_WIDTH(64)
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(64),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk),
@ -851,6 +868,8 @@ udp_payload_fifo (
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
@ -859,6 +878,8 @@ udp_payload_fifo (
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

4
example/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -72,10 +72,8 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_adapter.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo_64.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch_64_4x4.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch_4x4.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo_64.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

13
example/VCU108/fpga_1g/rtl/fpga_core.v
View File

@ -546,7 +546,12 @@ udp_complete_inst (
axis_fifo #(
.ADDR_WIDTH(12),
.DATA_WIDTH(8)
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
udp_payload_fifo (
.clk(clk),
@ -554,16 +559,22 @@ udp_payload_fifo (
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
);

32
rtl/eth_mac_10g_fifo.v
View File

@ -166,9 +166,18 @@ eth_mac_10g_inst (
.ifg_delay(ifg_delay)
);
axis_async_frame_fifo_64 #(
axis_async_frame_fifo #(
.ADDR_WIDTH(TX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(0)
)
tx_fifo (
@ -181,6 +190,8 @@ tx_fifo (
.input_axis_tvalid(tx_axis_tvalid),
.input_axis_tready(tx_axis_tready),
.input_axis_tlast(tx_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(tx_axis_tuser),
// AXI output
.output_clk(tx_clk),
@ -189,6 +200,9 @@ tx_fifo (
.output_axis_tvalid(tx_fifo_axis_tvalid),
.output_axis_tready(tx_fifo_axis_tready),
.output_axis_tlast(tx_fifo_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(tx_fifo_overflow),
.input_status_bad_frame(tx_fifo_bad_frame),
@ -200,9 +214,18 @@ tx_fifo (
assign tx_fifo_axis_tuser = 1'b0;
axis_async_frame_fifo_64 #(
axis_async_frame_fifo #(
.ADDR_WIDTH(RX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(1)
)
rx_fifo (
@ -215,6 +238,8 @@ rx_fifo (
.input_axis_tvalid(rx_fifo_axis_tvalid),
.input_axis_tready(),
.input_axis_tlast(rx_fifo_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.output_clk(logic_clk),
@ -223,6 +248,9 @@ rx_fifo (
.output_axis_tvalid(rx_axis_tvalid),
.output_axis_tready(rx_axis_tready),
.output_axis_tlast(rx_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(),
.input_status_bad_frame(),

26
rtl/eth_mac_1g_fifo.v
View File

@ -177,6 +177,14 @@ eth_mac_1g_inst (
axis_async_frame_fifo #(
.ADDR_WIDTH(TX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(0)
)
tx_fifo (
@ -188,6 +196,8 @@ tx_fifo (
.input_axis_tvalid(tx_axis_tvalid),
.input_axis_tready(tx_axis_tready),
.input_axis_tlast(tx_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(tx_axis_tuser),
// AXI output
.output_clk(tx_clk),
@ -195,6 +205,9 @@ tx_fifo (
.output_axis_tvalid(tx_fifo_axis_tvalid),
.output_axis_tready(tx_fifo_axis_tready),
.output_axis_tlast(tx_fifo_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(tx_fifo_overflow),
.input_status_bad_frame(tx_fifo_bad_frame),
@ -209,6 +222,14 @@ assign tx_fifo_axis_tuser = 1'b0;
axis_async_frame_fifo #(
.ADDR_WIDTH(RX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(1)
)
rx_fifo (
@ -220,6 +241,8 @@ rx_fifo (
.input_axis_tvalid(rx_fifo_axis_tvalid),
.input_axis_tready(),
.input_axis_tlast(rx_fifo_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.output_clk(logic_clk),
@ -227,6 +250,9 @@ rx_fifo (
.output_axis_tvalid(rx_axis_tvalid),
.output_axis_tready(rx_axis_tready),
.output_axis_tlast(rx_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(),
.input_status_bad_frame(),

26
rtl/eth_mac_1g_gmii_fifo.v
View File

@ -204,6 +204,14 @@ eth_mac_1g_gmii_inst (
axis_async_frame_fifo #(
.ADDR_WIDTH(TX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(0)
)
tx_fifo (
@ -215,6 +223,8 @@ tx_fifo (
.input_axis_tvalid(tx_axis_tvalid),
.input_axis_tready(tx_axis_tready),
.input_axis_tlast(tx_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(tx_axis_tuser),
// AXI output
.output_clk(tx_clk),
@ -222,6 +232,9 @@ tx_fifo (
.output_axis_tvalid(tx_fifo_axis_tvalid),
.output_axis_tready(tx_fifo_axis_tready),
.output_axis_tlast(tx_fifo_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(tx_fifo_overflow),
.input_status_bad_frame(tx_fifo_bad_frame),
@ -236,6 +249,14 @@ assign tx_fifo_axis_tuser = 1'b0;
axis_async_frame_fifo #(
.ADDR_WIDTH(RX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(1)
)
rx_fifo (
@ -247,6 +268,8 @@ rx_fifo (
.input_axis_tvalid(rx_fifo_axis_tvalid),
.input_axis_tready(),
.input_axis_tlast(rx_fifo_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.output_clk(logic_clk),
@ -254,6 +277,9 @@ rx_fifo (
.output_axis_tvalid(rx_axis_tvalid),
.output_axis_tready(rx_axis_tready),
.output_axis_tlast(rx_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(),
.input_status_bad_frame(),

26
rtl/eth_mac_1g_rgmii_fifo.v
View File

@ -203,6 +203,14 @@ eth_mac_1g_rgmii_inst (
axis_async_frame_fifo #(
.ADDR_WIDTH(TX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(0)
)
tx_fifo (
@ -214,6 +222,8 @@ tx_fifo (
.input_axis_tvalid(tx_axis_tvalid),
.input_axis_tready(tx_axis_tready),
.input_axis_tlast(tx_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(tx_axis_tuser),
// AXI output
.output_clk(tx_clk),
@ -221,6 +231,9 @@ tx_fifo (
.output_axis_tvalid(tx_fifo_axis_tvalid),
.output_axis_tready(tx_fifo_axis_tready),
.output_axis_tlast(tx_fifo_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(tx_fifo_overflow),
.input_status_bad_frame(tx_fifo_bad_frame),
@ -235,6 +248,14 @@ assign tx_fifo_axis_tuser = 1'b0;
axis_async_frame_fifo #(
.ADDR_WIDTH(RX_FIFO_ADDR_WIDTH),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(1)
)
rx_fifo (
@ -246,6 +267,8 @@ rx_fifo (
.input_axis_tvalid(rx_fifo_axis_tvalid),
.input_axis_tready(),
.input_axis_tlast(rx_fifo_axis_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.output_clk(logic_clk),
@ -253,6 +276,9 @@ rx_fifo (
.output_axis_tvalid(rx_axis_tvalid),
.output_axis_tready(rx_axis_tready),
.output_axis_tlast(rx_axis_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(),
// Status
.input_status_overflow(),
.input_status_bad_frame(),

14
rtl/udp_checksum_gen.v
View File

@ -197,23 +197,35 @@ wire output_udp_payload_fifo_tlast;
wire output_udp_payload_fifo_tuser;
axis_fifo #(
.ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH),
.DATA_WIDTH(8),
.ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH)
.KEEP_ENABLE(0),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_udp_payload_fifo_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(input_udp_payload_fifo_tvalid),
.input_axis_tready(input_udp_payload_fifo_tready),
.input_axis_tlast(input_udp_payload_fifo_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(input_udp_payload_fifo_tuser),
// AXI output
.output_axis_tdata(output_udp_payload_fifo_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(output_udp_payload_fifo_tvalid),
.output_axis_tready(output_udp_payload_fifo_tready),
.output_axis_tlast(output_udp_payload_fifo_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(output_udp_payload_fifo_tuser)
);

15
rtl/udp_checksum_gen_64.v
View File

@ -201,9 +201,16 @@ wire output_udp_payload_fifo_tready;
wire output_udp_payload_fifo_tlast;
wire output_udp_payload_fifo_tuser;
axis_fifo_64 #(
axis_fifo #(
.ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH),
.DATA_WIDTH(64),
.ADDR_WIDTH(PAYLOAD_FIFO_ADDR_WIDTH)
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
payload_fifo (
.clk(clk),
@ -214,6 +221,8 @@ payload_fifo (
.input_axis_tvalid(input_udp_payload_fifo_tvalid),
.input_axis_tready(input_udp_payload_fifo_tready),
.input_axis_tlast(input_udp_payload_fifo_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(input_udp_payload_fifo_tuser),
// AXI output
.output_axis_tdata(output_udp_payload_fifo_tdata),
@ -221,6 +230,8 @@ payload_fifo (
.output_axis_tvalid(output_udp_payload_fifo_tvalid),
.output_axis_tready(output_udp_payload_fifo_tready),
.output_axis_tlast(output_udp_payload_fifo_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(output_udp_payload_fifo_tuser)
);

2
tb/test_eth_mac_10g_fifo.py
View File

@ -40,7 +40,7 @@ srcs.append("../rtl/lfsr.v")
srcs.append("../rtl/eth_mac_10g_rx.v")
srcs.append("../rtl/eth_mac_10g_tx.v")
srcs.append("../rtl/eth_mac_10g.v")
srcs.append("../lib/axis/rtl/axis_async_frame_fifo_64.v")
srcs.append("../lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
tb/test_eth_mac_10g_rx.py
View File

@ -354,7 +354,7 @@ def bench():
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
rx_frame = sink.recv()

2
tb/test_eth_mac_10g_tx.py
View File

@ -272,7 +272,7 @@ def bench():
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.user = 1
axis_frame1.last_cycle_user = 1
source.send(axis_frame1)
source.send(axis_frame2)

2
tb/test_eth_mac_1g_rx.py
View File

@ -350,7 +350,7 @@ def bench():
rx_frame = sink.recv()
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
rx_frame = sink.recv()

2
tb/test_eth_mac_1g_tx.py
View File

@ -272,7 +272,7 @@ def bench():
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.user = 1
axis_frame1.last_cycle_user = 1
source.send(axis_frame1)
source.send(axis_frame2)

2
tb/test_udp_64.py
View File

@ -39,7 +39,7 @@ srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/udp_checksum_gen_64.v")
srcs.append("../rtl/udp_ip_rx_64.v")
srcs.append("../rtl/udp_ip_tx_64.v")
srcs.append("../lib/axis/rtl/axis_fifo_64.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
tb/test_udp_checksum_gen_64.py
View File

@ -37,7 +37,7 @@ testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../lib/axis/rtl/axis_fifo_64.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
tb/test_udp_complete_64.py
View File

@ -55,7 +55,7 @@ srcs.append("../rtl/eth_arb_mux_64_2.v")
srcs.append("../rtl/eth_mux_64_2.v")
srcs.append("../lib/axis/rtl/arbiter.v")
srcs.append("../lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/axis/rtl/axis_fifo_64.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)