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https://github.com/alexforencich/verilog-ethernet.git
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Fix error detect in 1G MAC
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13afff6686
commit
bfc97ac311
@ -143,7 +143,7 @@ always @* begin
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output_axis_tdata_next = gmii_rxd_d4;
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output_axis_tvalid_next = 1;
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if (gmii_rx_dv & gmii_rx_er) begin
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if (gmii_rx_dv_d4 & gmii_rx_er_d4) begin
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// error
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output_axis_tlast_next = 1;
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output_axis_tuser_next = 1;
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@ -152,7 +152,11 @@ always @* begin
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end else if (~gmii_rx_dv) begin
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// end of packet
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output_axis_tlast_next = 1;
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if ({gmii_rxd_d0, gmii_rxd_d1, gmii_rxd_d2, gmii_rxd_d3} == ~crc_next) begin
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if (gmii_rx_er_d0 | gmii_rx_er_d1 | gmii_rx_er_d2 | gmii_rx_er_d3) begin
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// error received in FCS bytes
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output_axis_tuser_next = 1;
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error_bad_frame_next = 1;
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end else if ({gmii_rxd_d0, gmii_rxd_d1, gmii_rxd_d2, gmii_rxd_d3} == ~crc_next) begin
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// FCS good
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output_axis_tuser_next = 0;
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end else begin
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