FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity

Update example design readmes

Browse Source
This commit is contained in:
Alex Forencich 2021-05-04 15:48:12 -07:00
parent 2796e681c9
commit c021d01c26
32 changed files with 299 additions and 132 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
example/ADM_PCIE_9V3/fpga_10g/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcvu3p-ffvc1517-2-i
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcvu3p-ffvc1517-2-i
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -19,6 +19,12 @@ in PATH.
## How to test
Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

14
example/ADM_PCIE_9V3/fpga_25g/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcvu3p-ffvc1517-2-i
PHY: 25G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcvu3p-ffvc1517-2-i
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -19,6 +19,12 @@ in PATH.
## How to test
Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/ATLYS/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: XC6SLX45CSG324-2
PHY: Marvell 88E1111
* FPGA: XC6SLX45CSG324-2
* PHY: Marvell 88E1111
## How to build
@ -19,8 +19,13 @@ in PATH.
## How to test
Run make program to program the Atlys board with the Digilent command line
tools. Then run netcat -u 192.168.1.128 1234 to open a UDP connection to
port 1234. Any text entered into netcat will be echoed back after pressing
enter.
tools. Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

16
example/AU200/fpga_10g/README.md
View File

@ -6,11 +6,10 @@ This example design targets the Xilinx Alveo U200 FPGA board.
The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests. The design also enables the gigabit Ethernet interface for
testing with a QSFP loopback adapter.
to ARP requests.
FPGA: xcu200-fsgd2104-2-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcu200-fsgd2104-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -20,7 +19,12 @@ in PATH.
## How to test
Run make program to program the Alveo U200 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

16
example/AU250/fpga_10g/README.md
View File

@ -6,11 +6,10 @@ This example design targets the Xilinx Alveo U250 FPGA board.
The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests. The design also enables the gigabit Ethernet interface for
testing with a QSFP loopback adapter.
to ARP requests.
FPGA: xcu250-figd2104-2-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcu250-figd2104-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -20,7 +19,12 @@ in PATH.
## How to test
Run make program to program the Alveo U250 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

9
example/AU280/fpga_10g/README.md
View File

@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the Alveo U280 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

9
example/AU50/fpga_10g/README.md
View File

@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the Alveo U50 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/Arty/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: XC7A35TICSG324-1L
PHY: TI DP83848J
* FPGA: XC7A35TICSG324-1L
* PHY: TI DP83848J
## How to build
@ -18,8 +18,13 @@ in PATH.
## How to test
Run make program to program the Arty board with Vivado. Then run netcat -u
192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered
into netcat will be echoed back after pressing enter.
Run make program to program the Arty board with Vivado. Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

13
example/C10LP/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: 5SGXEA7N2F45C2
PHY: Intel XWAY PHY11G PEF7071
* FPGA: 5SGXEA7N2F45C2
* PHY: Intel XWAY PHY11G PEF7071
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the board with the Altera software. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any
text entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

13
example/DE2-115/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: EP4CE115F29C7
PHY: Marvell Alaska 88E1111
* FPGA: EP4CE115F29C7
* PHY: Marvell Alaska 88E1111
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the board with the Altera software. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any
text entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

14
example/DE5-Net/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: 5SGXEA7N2F45C2
PHY: 10G BASE-R PHY MegaCore
* FPGA: 5SGXEA7N2F45C2
* PHY: 10G BASE-R PHY MegaCore
## How to build
@ -19,7 +19,13 @@ in PATH.
## How to test
Run make program to program the DE5-Net board with the Altera software. Then
run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any
text entered into netcat will be echoed back after pressing enter.
run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

13
example/ExaNIC_X10/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcku035-fbva676-2-c
PHY: 10G BASE-R PHY IP core and internal GTH transceiver
* FPGA: xcku035-fbva676-2-c
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the ExaNIC X10 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

13
example/ExaNIC_X25/fpga_10g/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcku3p-ffvb676-2-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcku3p-ffvb676-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the ExaNIC X25 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

14
example/HXT100G/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: XC6VHX565T-2FFG1923
PHY: 10G BASE-R PHY IP core and internal GTH transceiver
* FPGA: XC6VHX565T-2FFG1923
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build
@ -19,7 +19,13 @@ in PATH.
## How to test
Run make program to program the HXT100G board with the Xilinx Impact software.
Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234.
Anyntext entered into netcat will be echoed back after pressing enter.
Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

4
example/HXT100G/fpga_cxpt16/README.md
View File

@ -8,8 +8,8 @@ The design forms a 16x16 crosspoint switch for 10G Ethernet. It is capable of
connecting any output port to any input port based on configuration frames
received over a dedicated configuration interface.
FPGA: XC6VHX565T-2FFG1923
PHY: 10G BASE-R PHY IP core and internal GTH transceiver
* FPGA: XC6VHX565T-2FFG1923
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build

15
example/KC705/fpga_gmii/README.md
View File

@ -11,8 +11,8 @@ to ARP requests.
Configure the PHY for GMII by placing J29 and J30 across pins 1 and 2 and
opening J64.
FPGA: XC7K325T-2FFG900C
PHY: Marvell 88E1111
* FPGA: XC7K325T-2FFG900C
* PHY: Marvell 88E1111
## How to build
@ -21,8 +21,13 @@ in PATH.
## How to test
Run make program to program the KC705 board with Vivado. Then run netcat -u
192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered
into netcat will be echoed back after pressing enter.
Run make program to program the KC705 board with Vivado. Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/KC705/fpga_rgmii/README.md
View File

@ -11,8 +11,8 @@ to ARP requests.
Configure the PHY for RGMII by placing J29 across pins 1 and 2, opening J30,
and shorting J64.
FPGA: XC7K325T-2FFG900C
PHY: Marvell 88E1111
* FPGA: XC7K325T-2FFG900C
* PHY: Marvell 88E1111
## How to build
@ -21,8 +21,13 @@ in PATH.
## How to test
Run make program to program the KC705 board with Vivado. Then run netcat -u
192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered
into netcat will be echoed back after pressing enter.
Run make program to program the KC705 board with Vivado. Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/KC705/fpga_sgmii/README.md
View File

@ -11,8 +11,8 @@ to ARP requests.
Configure the PHY for SGMII by placing J29 and J30 across pins 2 and 3 and
opening J64.
FPGA: XC7K325T-2FFG900C
PHY: Marvell 88E1111
* FPGA: XC7K325T-2FFG900C
* PHY: Marvell 88E1111
## How to build
@ -21,8 +21,13 @@ in PATH.
## How to test
Run make program to program the KC705 board with Vivado. Then run netcat -u
192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered
into netcat will be echoed back after pressing enter.
Run make program to program the KC705 board with Vivado. Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

14
example/ML605/fpga_gmii/README.md
View File

@ -11,8 +11,8 @@ to ARP requests.
Configure the PHY for GMII by placing J66 and J67 across pins 1 and 2 and
opening J68.
FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156
PHY: Marvell M88E1111
* FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156
* PHY: Marvell M88E1111
## How to build
@ -22,7 +22,13 @@ in PATH.
## How to test
Run make program to program the ML605 board with the Xilinx Impact software.
Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234.
Any text entered into netcat will be echoed back after pressing enter.
Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

14
example/ML605/fpga_rgmii/README.md
View File

@ -11,8 +11,8 @@ to ARP requests.
Configure the PHY for RGMII by placing J66 across pins 1 and 2, opening J67,
and shorting J68.
FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156
PHY: Marvell M88E1111
* FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156
* PHY: Marvell M88E1111
## How to build
@ -22,7 +22,13 @@ in PATH.
## How to test
Run make program to program the ML605 board with the Xilinx Impact software.
Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234.
Any text entered into netcat will be echoed back after pressing enter.
Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

14
example/ML605/fpga_sgmii/README.md
View File

@ -11,8 +11,8 @@ to ARP requests.
Configure the PHY for SGMII by placing J66 and J67 across pins 2 and 3 and
opening J68.
FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156
PHY: Marvell M88E1111
* FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156
* PHY: Marvell M88E1111
## How to build
@ -22,7 +22,13 @@ in PATH.
## How to test
Run make program to program the ML605 board with the Xilinx Impact software.
Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234.
Any text entered into netcat will be echoed back after pressing enter.
Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

13
example/NetFPGA_SUME/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xc7vx690tffg1761-3
PHY: 10G BASE-R PHY IP core and internal GTH transceiver
* FPGA: xc7vx690tffg1761-3
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the NetFPGA SUME board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/NexysVideo/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: XC7A200TSBG484-1
PHY: Realtek RTL8211E
* FPGA: XC7A200TSBG484-1
* PHY: Realtek RTL8211E
## How to build
@ -19,8 +19,13 @@ in PATH.
## How to test
Run make program to program the Nexys Video board with the Digilent command
line tools. Then run netcat -u 192.168.1.128 1234 to open a UDP connection to
port 1234. Any text entered into netcat will be echoed back after pressing
enter.
line tools. Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/VCU108/fpga_10g/README.md
View File

@ -9,8 +9,8 @@ will echo back any packets received. The design will also respond correctly
to ARP requests. The design also enables the gigabit Ethernet interface for
testing with a QSFP loopback adapter.
FPGA: xcvu095-ffva2104-2-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcvu095-ffva2104-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -20,8 +20,15 @@ in PATH.
## How to test
Run make program to program the VCU108 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024
Note that the gigabit PHY is also enabled for debugging. The gigabit port can
be inserted into the 10G data path between the 10G MAC and 10G PHY so that the

13
example/VCU108/fpga_1g/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcvu095-ffva2104-2-e
PHY: Marvell M88E1111
* FPGA: xcvu095-ffva2104-2-e
* PHY: Marvell M88E1111
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the VCU108 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/VCU118/fpga_10g/README.md
View File

@ -9,8 +9,8 @@ will echo back any packets received. The design will also respond correctly
to ARP requests. The design also enables the gigabit Ethernet interface for
testing with a QSFP loopback adapter.
FPGA: xcvu9p-flga2104-2L-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcvu9p-flga2104-2L-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -20,8 +20,15 @@ in PATH.
## How to test
Run make program to program the VCU118 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024
Note that the gigabit PHY is also enabled for debugging. The gigabit port can
be inserted into the 10G data path between the 10G MAC and 10G PHY so that the

13
example/VCU118/fpga_1g/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcvu9p-flga2104-2L-e
PHY: TI DP83867ISRGZ
* FPGA: xcvu9p-flga2104-2L-e
* PHY: TI DP83867ISRGZ
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the VCU108 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

15
example/VCU118/fpga_25g/README.md
View File

@ -9,8 +9,8 @@ will echo back any packets received. The design will also respond correctly
to ARP requests. The design also enables the gigabit Ethernet interface for
testing with a QSFP loopback adapter.
FPGA: xcvu9p-flga2104-2L-e
PHY: 25G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcvu9p-flga2104-2L-e
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -20,8 +20,15 @@ in PATH.
## How to test
Run make program to program the VCU118 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024
Note that the gigabit PHY is also enabled for debugging. The gigabit port can
be inserted into the 25G data path between the 25G MAC and 25G PHY so that the

13
example/VCU1525/fpga_10g/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcvu9p-fsgd2104-2L-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcvu9p-fsgd2104-2L-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the VCU1525 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

13
example/ZCU102/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xczu9eg-ffvb1156-2-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xczu9eg-ffvb1156-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the ZCU102 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

13
example/ZCU106/fpga/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xczu7ev-ffvc1156-2-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xczu7ev-ffvc1156-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -19,7 +19,12 @@ in PATH.
## How to test
Run make program to program the ZCU106 board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024

14
example/fb2CG/fpga_10g/README.md
View File

@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
FPGA: xcku15p-ffve1760-2-e
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
* FPGA: xcku15p-ffve1760-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
@ -19,6 +19,12 @@ in PATH.
## How to test
Run make program to program the fb2CG@KU15P board with Vivado. Then run
netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
entered into netcat will be echoed back after pressing enter.
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024