From c021d01c26d4cbb4682c5fed0891107effaf0865 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 4 May 2021 15:48:12 -0700 Subject: [PATCH] Update example design readmes --- example/ADM_PCIE_9V3/fpga_10g/README.md | 14 ++++++++++---- example/ADM_PCIE_9V3/fpga_25g/README.md | 14 ++++++++++---- example/ATLYS/fpga/README.md | 15 ++++++++++----- example/AU200/fpga_10g/README.md | 16 ++++++++++------ example/AU250/fpga_10g/README.md | 16 ++++++++++------ example/AU280/fpga_10g/README.md | 9 +++++++-- example/AU50/fpga_10g/README.md | 9 +++++++-- example/Arty/fpga/README.md | 15 ++++++++++----- example/C10LP/fpga/README.md | 13 +++++++++---- example/DE2-115/fpga/README.md | 13 +++++++++---- example/DE5-Net/fpga/README.md | 14 ++++++++++---- example/ExaNIC_X10/fpga/README.md | 13 +++++++++---- example/ExaNIC_X25/fpga_10g/README.md | 13 +++++++++---- example/HXT100G/fpga/README.md | 14 ++++++++++---- example/HXT100G/fpga_cxpt16/README.md | 4 ++-- example/KC705/fpga_gmii/README.md | 15 ++++++++++----- example/KC705/fpga_rgmii/README.md | 15 ++++++++++----- example/KC705/fpga_sgmii/README.md | 15 ++++++++++----- example/ML605/fpga_gmii/README.md | 14 ++++++++++---- example/ML605/fpga_rgmii/README.md | 14 ++++++++++---- example/ML605/fpga_sgmii/README.md | 14 ++++++++++---- example/NetFPGA_SUME/fpga/README.md | 13 +++++++++---- example/NexysVideo/fpga/README.md | 15 ++++++++++----- example/VCU108/fpga_10g/README.md | 15 +++++++++++---- example/VCU108/fpga_1g/README.md | 13 +++++++++---- example/VCU118/fpga_10g/README.md | 15 +++++++++++---- example/VCU118/fpga_1g/README.md | 13 +++++++++---- example/VCU118/fpga_25g/README.md | 15 +++++++++++---- example/VCU1525/fpga_10g/README.md | 13 +++++++++---- example/ZCU102/fpga/README.md | 13 +++++++++---- example/ZCU106/fpga/README.md | 13 +++++++++---- example/fb2CG/fpga_10g/README.md | 14 ++++++++++---- 32 files changed, 299 insertions(+), 132 deletions(-) diff --git a/example/ADM_PCIE_9V3/fpga_10g/README.md b/example/ADM_PCIE_9V3/fpga_10g/README.md index 89881d19..10a48174 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/README.md +++ b/example/ADM_PCIE_9V3/fpga_10g/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcvu3p-ffvc1517-2-i -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu3p-ffvc1517-2-i +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -19,6 +19,12 @@ in PATH. ## How to test Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ADM_PCIE_9V3/fpga_25g/README.md b/example/ADM_PCIE_9V3/fpga_25g/README.md index 691f825b..8420f0d8 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/README.md +++ b/example/ADM_PCIE_9V3/fpga_25g/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcvu3p-ffvc1517-2-i -PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu3p-ffvc1517-2-i +* PHY: 25G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -19,6 +19,12 @@ in PATH. ## How to test Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ATLYS/fpga/README.md b/example/ATLYS/fpga/README.md index e028eda6..cceeb9c6 100644 --- a/example/ATLYS/fpga/README.md +++ b/example/ATLYS/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: XC6SLX45CSG324-2 -PHY: Marvell 88E1111 +* FPGA: XC6SLX45CSG324-2 +* PHY: Marvell 88E1111 ## How to build @@ -19,8 +19,13 @@ in PATH. ## How to test Run make program to program the Atlys board with the Digilent command line -tools. Then run netcat -u 192.168.1.128 1234 to open a UDP connection to -port 1234. Any text entered into netcat will be echoed back after pressing -enter. +tools. Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/AU200/fpga_10g/README.md b/example/AU200/fpga_10g/README.md index 24decdba..b69b5a8a 100644 --- a/example/AU200/fpga_10g/README.md +++ b/example/AU200/fpga_10g/README.md @@ -6,11 +6,10 @@ This example design targets the Xilinx Alveo U200 FPGA board. The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly -to ARP requests. The design also enables the gigabit Ethernet interface for -testing with a QSFP loopback adapter. +to ARP requests. -FPGA: xcu200-fsgd2104-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcu200-fsgd2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -20,7 +19,12 @@ in PATH. ## How to test Run make program to program the Alveo U200 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/AU250/fpga_10g/README.md b/example/AU250/fpga_10g/README.md index a901cd90..d8c2fea6 100644 --- a/example/AU250/fpga_10g/README.md +++ b/example/AU250/fpga_10g/README.md @@ -6,11 +6,10 @@ This example design targets the Xilinx Alveo U250 FPGA board. The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly -to ARP requests. The design also enables the gigabit Ethernet interface for -testing with a QSFP loopback adapter. +to ARP requests. -FPGA: xcu250-figd2104-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcu250-figd2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -20,7 +19,12 @@ in PATH. ## How to test Run make program to program the Alveo U250 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/AU280/fpga_10g/README.md b/example/AU280/fpga_10g/README.md index 0d366bea..c1e7939d 100644 --- a/example/AU280/fpga_10g/README.md +++ b/example/AU280/fpga_10g/README.md @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the Alveo U280 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/AU50/fpga_10g/README.md b/example/AU50/fpga_10g/README.md index 4ba92522..fb97196d 100644 --- a/example/AU50/fpga_10g/README.md +++ b/example/AU50/fpga_10g/README.md @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the Alveo U50 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/Arty/fpga/README.md b/example/Arty/fpga/README.md index 75c85233..1b30422d 100644 --- a/example/Arty/fpga/README.md +++ b/example/Arty/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: XC7A35TICSG324-1L -PHY: TI DP83848J +* FPGA: XC7A35TICSG324-1L +* PHY: TI DP83848J ## How to build @@ -18,8 +18,13 @@ in PATH. ## How to test -Run make program to program the Arty board with Vivado. Then run netcat -u -192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered -into netcat will be echoed back after pressing enter. +Run make program to program the Arty board with Vivado. Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/C10LP/fpga/README.md b/example/C10LP/fpga/README.md index 70110cf3..8c0d072a 100644 --- a/example/C10LP/fpga/README.md +++ b/example/C10LP/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: 5SGXEA7N2F45C2 -PHY: Intel XWAY PHY11G PEF7071 +* FPGA: 5SGXEA7N2F45C2 +* PHY: Intel XWAY PHY11G PEF7071 ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the board with the Altera software. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any -text entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/DE2-115/fpga/README.md b/example/DE2-115/fpga/README.md index bdca5c69..7590009f 100644 --- a/example/DE2-115/fpga/README.md +++ b/example/DE2-115/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: EP4CE115F29C7 -PHY: Marvell Alaska 88E1111 +* FPGA: EP4CE115F29C7 +* PHY: Marvell Alaska 88E1111 ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the board with the Altera software. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any -text entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/DE5-Net/fpga/README.md b/example/DE5-Net/fpga/README.md index 07c43c16..7c362bca 100644 --- a/example/DE5-Net/fpga/README.md +++ b/example/DE5-Net/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: 5SGXEA7N2F45C2 -PHY: 10G BASE-R PHY MegaCore +* FPGA: 5SGXEA7N2F45C2 +* PHY: 10G BASE-R PHY MegaCore ## How to build @@ -19,7 +19,13 @@ in PATH. ## How to test Run make program to program the DE5-Net board with the Altera software. Then -run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any -text entered into netcat will be echoed back after pressing enter. +run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ExaNIC_X10/fpga/README.md b/example/ExaNIC_X10/fpga/README.md index c11efb3d..93191ab3 100644 --- a/example/ExaNIC_X10/fpga/README.md +++ b/example/ExaNIC_X10/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcku035-fbva676-2-c -PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* FPGA: xcku035-fbva676-2-c +* PHY: 10G BASE-R PHY IP core and internal GTH transceiver ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the ExaNIC X10 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ExaNIC_X25/fpga_10g/README.md b/example/ExaNIC_X25/fpga_10g/README.md index 1294c2d5..8b20b7a0 100644 --- a/example/ExaNIC_X25/fpga_10g/README.md +++ b/example/ExaNIC_X25/fpga_10g/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcku3p-ffvb676-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcku3p-ffvb676-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the ExaNIC X25 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/HXT100G/fpga/README.md b/example/HXT100G/fpga/README.md index 9da6d1a3..2a46b710 100644 --- a/example/HXT100G/fpga/README.md +++ b/example/HXT100G/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: XC6VHX565T-2FFG1923 -PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* FPGA: XC6VHX565T-2FFG1923 +* PHY: 10G BASE-R PHY IP core and internal GTH transceiver ## How to build @@ -19,7 +19,13 @@ in PATH. ## How to test Run make program to program the HXT100G board with the Xilinx Impact software. -Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. -Anyntext entered into netcat will be echoed back after pressing enter. +Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/HXT100G/fpga_cxpt16/README.md b/example/HXT100G/fpga_cxpt16/README.md index 1128f97c..c31e812a 100644 --- a/example/HXT100G/fpga_cxpt16/README.md +++ b/example/HXT100G/fpga_cxpt16/README.md @@ -8,8 +8,8 @@ The design forms a 16x16 crosspoint switch for 10G Ethernet. It is capable of connecting any output port to any input port based on configuration frames received over a dedicated configuration interface. -FPGA: XC6VHX565T-2FFG1923 -PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* FPGA: XC6VHX565T-2FFG1923 +* PHY: 10G BASE-R PHY IP core and internal GTH transceiver ## How to build diff --git a/example/KC705/fpga_gmii/README.md b/example/KC705/fpga_gmii/README.md index e524f627..e1edc1e0 100644 --- a/example/KC705/fpga_gmii/README.md +++ b/example/KC705/fpga_gmii/README.md @@ -11,8 +11,8 @@ to ARP requests. Configure the PHY for GMII by placing J29 and J30 across pins 1 and 2 and opening J64. -FPGA: XC7K325T-2FFG900C -PHY: Marvell 88E1111 +* FPGA: XC7K325T-2FFG900C +* PHY: Marvell 88E1111 ## How to build @@ -21,8 +21,13 @@ in PATH. ## How to test -Run make program to program the KC705 board with Vivado. Then run netcat -u -192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered -into netcat will be echoed back after pressing enter. +Run make program to program the KC705 board with Vivado. Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/KC705/fpga_rgmii/README.md b/example/KC705/fpga_rgmii/README.md index b5b9eac9..83101985 100644 --- a/example/KC705/fpga_rgmii/README.md +++ b/example/KC705/fpga_rgmii/README.md @@ -11,8 +11,8 @@ to ARP requests. Configure the PHY for RGMII by placing J29 across pins 1 and 2, opening J30, and shorting J64. -FPGA: XC7K325T-2FFG900C -PHY: Marvell 88E1111 +* FPGA: XC7K325T-2FFG900C +* PHY: Marvell 88E1111 ## How to build @@ -21,8 +21,13 @@ in PATH. ## How to test -Run make program to program the KC705 board with Vivado. Then run netcat -u -192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered -into netcat will be echoed back after pressing enter. +Run make program to program the KC705 board with Vivado. Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/KC705/fpga_sgmii/README.md b/example/KC705/fpga_sgmii/README.md index 25cf7da6..e627a09b 100644 --- a/example/KC705/fpga_sgmii/README.md +++ b/example/KC705/fpga_sgmii/README.md @@ -11,8 +11,8 @@ to ARP requests. Configure the PHY for SGMII by placing J29 and J30 across pins 2 and 3 and opening J64. -FPGA: XC7K325T-2FFG900C -PHY: Marvell 88E1111 +* FPGA: XC7K325T-2FFG900C +* PHY: Marvell 88E1111 ## How to build @@ -21,8 +21,13 @@ in PATH. ## How to test -Run make program to program the KC705 board with Vivado. Then run netcat -u -192.168.1.128 1234 to open a UDP connection to port 1234. Any text entered -into netcat will be echoed back after pressing enter. +Run make program to program the KC705 board with Vivado. Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ML605/fpga_gmii/README.md b/example/ML605/fpga_gmii/README.md index 730a2f87..1ce4d419 100644 --- a/example/ML605/fpga_gmii/README.md +++ b/example/ML605/fpga_gmii/README.md @@ -11,8 +11,8 @@ to ARP requests. Configure the PHY for GMII by placing J66 and J67 across pins 1 and 2 and opening J68. -FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 -PHY: Marvell M88E1111 +* FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 +* PHY: Marvell M88E1111 ## How to build @@ -22,7 +22,13 @@ in PATH. ## How to test Run make program to program the ML605 board with the Xilinx Impact software. -Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. -Any text entered into netcat will be echoed back after pressing enter. +Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ML605/fpga_rgmii/README.md b/example/ML605/fpga_rgmii/README.md index 9602d184..1db5654d 100644 --- a/example/ML605/fpga_rgmii/README.md +++ b/example/ML605/fpga_rgmii/README.md @@ -11,8 +11,8 @@ to ARP requests. Configure the PHY for RGMII by placing J66 across pins 1 and 2, opening J67, and shorting J68. -FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 -PHY: Marvell M88E1111 +* FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 +* PHY: Marvell M88E1111 ## How to build @@ -22,7 +22,13 @@ in PATH. ## How to test Run make program to program the ML605 board with the Xilinx Impact software. -Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. -Any text entered into netcat will be echoed back after pressing enter. +Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ML605/fpga_sgmii/README.md b/example/ML605/fpga_sgmii/README.md index af3b0b23..6a65a89d 100644 --- a/example/ML605/fpga_sgmii/README.md +++ b/example/ML605/fpga_sgmii/README.md @@ -11,8 +11,8 @@ to ARP requests. Configure the PHY for SGMII by placing J66 and J67 across pins 2 and 3 and opening J68. -FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 -PHY: Marvell M88E1111 +* FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 +* PHY: Marvell M88E1111 ## How to build @@ -22,7 +22,13 @@ in PATH. ## How to test Run make program to program the ML605 board with the Xilinx Impact software. -Then run netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. -Any text entered into netcat will be echoed back after pressing enter. +Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/NetFPGA_SUME/fpga/README.md b/example/NetFPGA_SUME/fpga/README.md index e6f0cba7..4fd7d799 100644 --- a/example/NetFPGA_SUME/fpga/README.md +++ b/example/NetFPGA_SUME/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xc7vx690tffg1761-3 -PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* FPGA: xc7vx690tffg1761-3 +* PHY: 10G BASE-R PHY IP core and internal GTH transceiver ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the NetFPGA SUME board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/NexysVideo/fpga/README.md b/example/NexysVideo/fpga/README.md index e3ebba01..0a4553ea 100644 --- a/example/NexysVideo/fpga/README.md +++ b/example/NexysVideo/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: XC7A200TSBG484-1 -PHY: Realtek RTL8211E +* FPGA: XC7A200TSBG484-1 +* PHY: Realtek RTL8211E ## How to build @@ -19,8 +19,13 @@ in PATH. ## How to test Run make program to program the Nexys Video board with the Digilent command -line tools. Then run netcat -u 192.168.1.128 1234 to open a UDP connection to -port 1234. Any text entered into netcat will be echoed back after pressing -enter. +line tools. Then run + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/VCU108/fpga_10g/README.md b/example/VCU108/fpga_10g/README.md index fc508c33..aff3bd78 100644 --- a/example/VCU108/fpga_10g/README.md +++ b/example/VCU108/fpga_10g/README.md @@ -9,8 +9,8 @@ will echo back any packets received. The design will also respond correctly to ARP requests. The design also enables the gigabit Ethernet interface for testing with a QSFP loopback adapter. -FPGA: xcvu095-ffva2104-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu095-ffva2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -20,8 +20,15 @@ in PATH. ## How to test Run make program to program the VCU108 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 Note that the gigabit PHY is also enabled for debugging. The gigabit port can be inserted into the 10G data path between the 10G MAC and 10G PHY so that the diff --git a/example/VCU108/fpga_1g/README.md b/example/VCU108/fpga_1g/README.md index 196c6292..4bc276b7 100644 --- a/example/VCU108/fpga_1g/README.md +++ b/example/VCU108/fpga_1g/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcvu095-ffva2104-2-e -PHY: Marvell M88E1111 +* FPGA: xcvu095-ffva2104-2-e +* PHY: Marvell M88E1111 ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the VCU108 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/VCU118/fpga_10g/README.md b/example/VCU118/fpga_10g/README.md index c8beebca..25d58478 100644 --- a/example/VCU118/fpga_10g/README.md +++ b/example/VCU118/fpga_10g/README.md @@ -9,8 +9,8 @@ will echo back any packets received. The design will also respond correctly to ARP requests. The design also enables the gigabit Ethernet interface for testing with a QSFP loopback adapter. -FPGA: xcvu9p-flga2104-2L-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu9p-flga2104-2L-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -20,8 +20,15 @@ in PATH. ## How to test Run make program to program the VCU118 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 Note that the gigabit PHY is also enabled for debugging. The gigabit port can be inserted into the 10G data path between the 10G MAC and 10G PHY so that the diff --git a/example/VCU118/fpga_1g/README.md b/example/VCU118/fpga_1g/README.md index 66172f75..0c0a29e9 100644 --- a/example/VCU118/fpga_1g/README.md +++ b/example/VCU118/fpga_1g/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcvu9p-flga2104-2L-e -PHY: TI DP83867ISRGZ +* FPGA: xcvu9p-flga2104-2L-e +* PHY: TI DP83867ISRGZ ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the VCU108 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/VCU118/fpga_25g/README.md b/example/VCU118/fpga_25g/README.md index 4d972998..d8f7990d 100644 --- a/example/VCU118/fpga_25g/README.md +++ b/example/VCU118/fpga_25g/README.md @@ -9,8 +9,8 @@ will echo back any packets received. The design will also respond correctly to ARP requests. The design also enables the gigabit Ethernet interface for testing with a QSFP loopback adapter. -FPGA: xcvu9p-flga2104-2L-e -PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu9p-flga2104-2L-e +* PHY: 25G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -20,8 +20,15 @@ in PATH. ## How to test Run make program to program the VCU118 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 Note that the gigabit PHY is also enabled for debugging. The gigabit port can be inserted into the 25G data path between the 25G MAC and 25G PHY so that the diff --git a/example/VCU1525/fpga_10g/README.md b/example/VCU1525/fpga_10g/README.md index c482a9c8..0f7abfd9 100644 --- a/example/VCU1525/fpga_10g/README.md +++ b/example/VCU1525/fpga_10g/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcvu9p-fsgd2104-2L-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu9p-fsgd2104-2L-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the VCU1525 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ZCU102/fpga/README.md b/example/ZCU102/fpga/README.md index a6d10d5f..52d032f5 100644 --- a/example/ZCU102/fpga/README.md +++ b/example/ZCU102/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xczu9eg-ffvb1156-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xczu9eg-ffvb1156-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the ZCU102 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/ZCU106/fpga/README.md b/example/ZCU106/fpga/README.md index d449b7e7..a89d0d4e 100644 --- a/example/ZCU106/fpga/README.md +++ b/example/ZCU106/fpga/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xczu7ev-ffvc1156-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xczu7ev-ffvc1156-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -19,7 +19,12 @@ in PATH. ## How to test Run make program to program the ZCU106 board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/fb2CG/fpga_10g/README.md b/example/fb2CG/fpga_10g/README.md index 5f41827f..5ba234e1 100644 --- a/example/fb2CG/fpga_10g/README.md +++ b/example/fb2CG/fpga_10g/README.md @@ -8,8 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. -FPGA: xcku15p-ffve1760-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcku15p-ffve1760-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver ## How to build @@ -19,6 +19,12 @@ in PATH. ## How to test Run make program to program the fb2CG@KU15P board with Vivado. Then run -netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text -entered into netcat will be echoed back after pressing enter. + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be +echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024