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Add AXI stream frame length adjust modules

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Alex Forencich 2015-06-05 17:04:10 -07:00
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485
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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length adjuster
*/
module axis_frame_length_adjust #
(
parameter DATA_WIDTH = 1,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status
*/
output wire status_valid,
input wire status_ready,
output wire status_frame_pad,
output wire status_frame_truncate,
output wire [15:0] status_frame_length,
output wire [15:0] status_frame_original_length,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
// bus word width
localparam DATA_WORD_WIDTH = DATA_WIDTH / KEEP_WIDTH;
// bus width assertions
initial begin
if (DATA_WORD_WIDTH * KEEP_WIDTH != DATA_WIDTH) begin
$error("Error: data width not evenly divisble");
$finish;
end
end
// state register
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_TRANSFER = 3'd1,
STATE_PAD = 3'd2,
STATE_TRUNCATE = 3'd3;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_last_word;
reg [15:0] frame_ptr_reg = 0, frame_ptr_next;
reg [DATA_WIDTH-1:0] last_word_data_reg = 0;
reg [KEEP_WIDTH-1:0] last_word_keep_reg = 0;
reg last_cycle_tuser_reg = 0, last_cycle_tuser_next;
reg status_valid_reg = 0, status_valid_next;
reg status_frame_pad_reg = 0, status_frame_pad_next;
reg status_frame_truncate_reg = 0, status_frame_truncate_next;
reg [15:0] status_frame_length_reg = 0, status_frame_length_next;
reg [15:0] status_frame_original_length_reg = 0, status_frame_original_length_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
assign status_valid = status_valid_reg;
assign status_frame_pad = status_frame_pad_reg;
assign status_frame_truncate = status_frame_truncate_reg;
assign status_frame_length = status_frame_length_reg;
assign status_frame_original_length = status_frame_original_length_reg;
integer i, word_cnt;
always @* begin
state_next = STATE_IDLE;
store_last_word = 0;
frame_ptr_next = frame_ptr_reg;
output_axis_tdata_int = 0;
output_axis_tkeep_int = 0;
output_axis_tvalid_int = 0;
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
input_axis_tready_next = 0;
last_cycle_tuser_next = last_cycle_tuser_reg;
status_valid_next = status_valid_reg & ~status_ready;
status_frame_pad_next = status_frame_pad_reg;
status_frame_truncate_next = status_frame_truncate_reg;
status_frame_length_next = status_frame_length_reg;
status_frame_original_length_next = status_frame_original_length_reg;
case (state_reg)
STATE_IDLE: begin
// idle state
// accept data next cycle if output register ready next cycle
input_axis_tready_next = output_axis_tready_int_early & (~status_valid_reg | status_ready);
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin
// transfer through
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (input_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+word_cnt;
if (frame_ptr_next >= length_max) begin
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_max - frame_ptr_reg));
if (input_axis_tlast) begin
status_valid_next = 1;
status_frame_pad_next = 0;
status_frame_truncate_next = frame_ptr_next > length_max;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_next;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 0;
state_next = STATE_IDLE;
end else begin
output_axis_tvalid_int = 0;
store_last_word = 1;
state_next = STATE_TRUNCATE;
end
end else begin
if (input_axis_tlast) begin
status_frame_original_length_next = frame_ptr_next;
if (frame_ptr_next < length_min) begin
if (frame_ptr_reg + KEEP_WIDTH < length_min) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
input_axis_tready_next = 0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
last_cycle_tuser_next = input_axis_tuser;
state_next = STATE_PAD;
end else begin
status_valid_next = 1;
status_frame_pad_next = 1;
status_frame_truncate_next = 0;
status_frame_length_next = length_min;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_min - frame_ptr_reg));
frame_ptr_next = 0;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1;
status_frame_pad_next = 0;
status_frame_truncate_next = 0;
status_frame_length_next = frame_ptr_next;
status_frame_original_length_next = frame_ptr_next;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_TRANSFER: begin
// transfer data
// accept data next cycle if output register ready next cycle
input_axis_tready_next = output_axis_tready_int_early;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin
// transfer through
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (input_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+word_cnt;
if (frame_ptr_next >= length_max) begin
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_max - frame_ptr_reg));
if (input_axis_tlast) begin
status_valid_next = 1;
status_frame_pad_next = 0;
status_frame_truncate_next = frame_ptr_next > length_max;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_next;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 0;
state_next = STATE_IDLE;
end else begin
output_axis_tvalid_int = 0;
store_last_word = 1;
state_next = STATE_TRUNCATE;
end
end else begin
if (input_axis_tlast) begin
status_frame_original_length_next = frame_ptr_next;
if (frame_ptr_next < length_min) begin
if (frame_ptr_reg + KEEP_WIDTH < length_min) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
input_axis_tready_next = 0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
last_cycle_tuser_next = input_axis_tuser;
state_next = STATE_PAD;
end else begin
status_valid_next = 1;
status_frame_pad_next = 1;
status_frame_truncate_next = 0;
status_frame_length_next = length_min;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_min - frame_ptr_reg));
frame_ptr_next = 0;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1;
status_frame_pad_next = 0;
status_frame_truncate_next = 0;
status_frame_length_next = frame_ptr_next;
status_frame_original_length_next = frame_ptr_next;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
STATE_PAD: begin
// pad to minimum length
input_axis_tready_next = 0;
output_axis_tdata_int = 0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tvalid_int = 1;
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
if (output_axis_tready_int) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
if (frame_ptr_next >= length_min) begin
status_valid_next = 1;
status_frame_pad_next = 1;
status_frame_truncate_next = 0;
status_frame_length_next = length_min;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_min - frame_ptr_reg));
output_axis_tlast_int = 1;
output_axis_tuser_int = last_cycle_tuser_reg;
frame_ptr_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAD;
end
end else begin
state_next = STATE_PAD;
end
end
STATE_TRUNCATE: begin
// drop after maximum length
input_axis_tready_next = output_axis_tready_int_early;
output_axis_tdata_int = last_word_data_reg;
output_axis_tkeep_int = last_word_keep_reg;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tlast;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (input_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+word_cnt;
if (input_axis_tlast) begin
status_valid_next = 1;
status_frame_pad_next = 0;
status_frame_truncate_next = 1;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_next;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRUNCATE;
end
end else begin
state_next = STATE_TRUNCATE;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_axis_tready_reg <= 0;
last_word_data_reg <= 0;
last_word_keep_reg <= 0;
last_cycle_tuser_reg <= 0;
status_valid_reg <= 0;
status_frame_pad_reg <= 0;
status_frame_truncate_reg <= 0;
status_frame_length_reg <= 0;
status_frame_original_length_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
input_axis_tready_reg <= input_axis_tready_next;
last_cycle_tuser_reg <= last_cycle_tuser_next;
status_valid_reg <= status_valid_next;
status_frame_pad_reg <= status_frame_pad_next;
status_frame_truncate_reg <= status_frame_truncate_next;
status_frame_length_reg <= status_frame_length_next;
status_frame_original_length_reg <= status_frame_original_length_next;
if (store_last_word) begin
last_word_data_reg <= output_axis_tdata_int;
last_word_keep_reg <= output_axis_tkeep_int;
end
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tkeep_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready and currently valid, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length adjuster with FIFO
*/
module axis_frame_length_adjust_fifo #
(
parameter DATA_WIDTH = 8,
parameter FRAME_FIFO_ADDR_WIDTH = 12,
parameter HEADER_FIFO_ADDR_WIDTH = 3
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire output_axis_hdr_valid,
input wire output_axis_hdr_ready,
output wire output_axis_hdr_pad,
output wire output_axis_hdr_truncate,
output wire [15:0] output_axis_hdr_length,
output wire [15:0] output_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire fifo_axis_tuser;
wire status_valid;
wire status_ready;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(1)
)
axis_frame_length_adjust_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(1),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(fifo_axis_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(fifo_axis_tvalid),
.output_axis_tready(fifo_axis_tready),
.output_axis_tlast(fifo_axis_tlast),
.output_axis_tuser(fifo_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
axis_fifo #(
.ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
)
frame_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(fifo_axis_tdata),
.input_axis_tvalid(fifo_axis_tvalid),
.input_axis_tready(fifo_axis_tready),
.input_axis_tlast(fifo_axis_tlast),
.input_axis_tuser(fifo_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
axis_fifo #(
.ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
.DATA_WIDTH(1+1+16+16)
)
header_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.input_axis_tvalid(status_valid),
.input_axis_tready(status_ready),
.input_axis_tlast(0),
.input_axis_tuser(0),
// AXI output
.output_axis_tdata({output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length}),
.output_axis_tvalid(output_axis_hdr_valid),
.output_axis_tready(output_axis_hdr_ready),
.output_axis_tlast(),
.output_axis_tuser()
);
endmodule

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length adjuster with FIFO (64 bit datapath)
*/
module axis_frame_length_adjust_fifo_64 #
(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter FRAME_FIFO_ADDR_WIDTH = 12,
parameter HEADER_FIFO_ADDR_WIDTH = 3
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire output_axis_hdr_valid,
input wire output_axis_hdr_ready,
output wire output_axis_hdr_pad,
output wire output_axis_hdr_truncate,
output wire [15:0] output_axis_hdr_length,
output wire [15:0] output_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire fifo_axis_tuser;
wire status_valid;
wire status_ready;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
axis_frame_length_adjust_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(fifo_axis_tdata),
.output_axis_tkeep(fifo_axis_tkeep),
.output_axis_tvalid(fifo_axis_tvalid),
.output_axis_tready(fifo_axis_tready),
.output_axis_tlast(fifo_axis_tlast),
.output_axis_tuser(fifo_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
axis_fifo_64 #(
.ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
frame_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(fifo_axis_tdata),
.input_axis_tkeep(fifo_axis_tkeep),
.input_axis_tvalid(fifo_axis_tvalid),
.input_axis_tready(fifo_axis_tready),
.input_axis_tlast(fifo_axis_tlast),
.input_axis_tuser(fifo_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
axis_fifo #(
.ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
.DATA_WIDTH(1+1+16+16)
)
header_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.input_axis_tvalid(status_valid),
.input_axis_tready(status_ready),
.input_axis_tlast(0),
.input_axis_tuser(0),
// AXI output
.output_axis_tdata({output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length}),
.output_axis_tvalid(output_axis_hdr_valid),
.output_axis_tready(output_axis_hdr_ready),
.output_axis_tlast(),
.output_axis_tuser()
);
endmodule

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#!/usr/bin/env python
"""
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s_64.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s_64.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s_64.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
status_valid=status_valid,
status_ready=status_ready,
status_frame_pad=status_frame_pad,
status_frame_truncate=status_frame_truncate,
status_frame_length=status_frame_length,
status_frame_original_length=status_frame_original_length,
length_min=length_min,
length_max=length_max)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
status_ready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
length_max = Signal(intbv(0)[16:])
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
status_valid = Signal(bool(0))
status_frame_pad = Signal(bool(0))
status_frame_truncate = Signal(bool(0))
status_frame_length = Signal(intbv(0)[16:])
status_frame_original_length = Signal(intbv(0)[16:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
status_sink_queue = Queue()
status_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
status_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length),
tvalid=status_valid,
tready=status_ready,
fifo=status_sink_queue,
pause=status_sink_pause,
name='status_sink')
# DUT
dut = dut_axis_frame_length_adjust_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
length_min,
length_max)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while input_axis_tvalid or output_axis_tvalid:
yield clk.posedge
def wait_pause_source():
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
def wait_pause_sink():
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
length_min.next = 1
length_max.next = 20
for lmax in range(1,18):
for lmin in range(0,lmax+1):
length_min.next = lmin
length_max.next = lmax
for payload_len in range(1,18):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
assert rx_frame.user[-1]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, status_sink, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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tb/test_axis_frame_length_adjust_64.v Normal file
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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_length_adjust_64;
// parameters
localparam DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
status_ready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length);
// dump file
$dumpfile("test_axis_frame_length_adjust_64.lxt");
$dumpvars(0, test_axis_frame_length_adjust_64);
end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule

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tb/test_axis_frame_length_adjust_8.py Executable file
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#!/usr/bin/env python
"""
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s_8.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s_8.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_8(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s_8.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
status_valid=status_valid,
status_ready=status_ready,
status_frame_pad=status_frame_pad,
status_frame_truncate=status_frame_truncate,
status_frame_length=status_frame_length,
status_frame_original_length=status_frame_original_length,
length_min=length_min,
length_max=length_max)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tkeep = Signal(intbv(0)[1:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
status_ready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
length_max = Signal(intbv(0)[16:])
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tkeep = Signal(intbv(0)[1:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
status_valid = Signal(bool(0))
status_frame_pad = Signal(bool(0))
status_frame_truncate = Signal(bool(0))
status_frame_length = Signal(intbv(0)[16:])
status_frame_original_length = Signal(intbv(0)[16:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
status_sink_queue = Queue()
status_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
status_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length),
tvalid=status_valid,
tready=status_ready,
fifo=status_sink_queue,
pause=status_sink_pause,
name='status_sink')
# DUT
dut = dut_axis_frame_length_adjust_8(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_ready,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length,
length_min,
length_max)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while input_axis_tvalid or output_axis_tvalid:
yield clk.posedge
def wait_pause_source():
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
def wait_pause_sink():
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
length_min.next = 1
length_max.next = 20
for lmax in range(1,6):
for lmin in range(0,lmax+1):
length_min.next = lmin
length_max.next = lmax
for payload_len in range(1,6):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
assert rx_frame.user[-1]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink_queue.get(False)
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink_queue.get(False)
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink_queue.empty()
assert status_sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, status_sink, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_length_adjust_8;
// parameters
localparam DATA_WIDTH = 8;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
status_ready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length);
// dump file
$dumpfile("test_axis_frame_length_adjust_8.lxt");
$dumpvars(0, test_axis_frame_length_adjust_8);
end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule

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#!/usr/bin/env python
"""
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust_fifo'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_frame_length_adjust.v")
srcs.append("../rtl/axis_fifo.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_fifo(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid,
output_axis_hdr_ready=output_axis_hdr_ready,
output_axis_hdr_pad=output_axis_hdr_pad,
output_axis_hdr_truncate=output_axis_hdr_truncate,
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
length_max=length_max)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_hdr_ready = Signal(bool(0))
output_axis_tready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
length_max = Signal(intbv(0)[16:])
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_hdr_valid = Signal(bool(0))
output_axis_hdr_pad = Signal(bool(0))
output_axis_hdr_truncate = Signal(bool(0))
output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
hdr_sink_queue = Queue()
hdr_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
hdr_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length),
tvalid=output_axis_hdr_valid,
tready=output_axis_hdr_ready,
fifo=hdr_sink_queue,
pause=hdr_sink_pause,
name='hdr_sink')
# DUT
dut = dut_axis_frame_length_adjust_fifo(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
length_min,
length_max)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while input_axis_tvalid or output_axis_tvalid:
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
length_min.next = 1
length_max.next = 20
for lmax in range(1,6):
for lmin in range(0,lmax+1):
length_min.next = lmin
length_max.next = lmax
for payload_len in range(1,6):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1.user = 1
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, hdr_sink, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_length_adjust_fifo;
// parameters
localparam DATA_WIDTH = 8;
localparam FRAME_FIFO_ADDR_WIDTH = 12;
localparam HEADER_FIFO_ADDR_WIDTH = 3;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_hdr_ready = 0;
reg output_axis_tready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire output_axis_hdr_valid;
wire output_axis_hdr_pad;
wire output_axis_hdr_truncate;
wire [15:0] output_axis_hdr_length;
wire [15:0] output_axis_hdr_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_hdr_valid,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_frame_length_adjust_fifo.lxt");
$dumpvars(0, test_axis_frame_length_adjust_fifo);
end
axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_hdr_valid(output_axis_hdr_valid),
.output_axis_hdr_ready(output_axis_hdr_ready),
.output_axis_hdr_pad(output_axis_hdr_pad),
.output_axis_hdr_truncate(output_axis_hdr_truncate),
.output_axis_hdr_length(output_axis_hdr_length),
.output_axis_hdr_original_length(output_axis_hdr_original_length),
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule

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tb/test_axis_frame_length_adjust_fifo_64.py Executable file
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#!/usr/bin/env python
"""
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
try:
from queue import Queue
except ImportError:
from Queue import Queue
import axis_ep
module = 'axis_frame_length_adjust_fifo_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_frame_length_adjust.v")
srcs.append("../rtl/axis_fifo.v")
srcs.append("../rtl/axis_fifo_64.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_frame_length_adjust_fifo_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
length_min,
length_max):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid,
output_axis_hdr_ready=output_axis_hdr_ready,
output_axis_hdr_pad=output_axis_hdr_pad,
output_axis_hdr_truncate=output_axis_hdr_truncate,
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
length_max=length_max)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_hdr_ready = Signal(bool(0))
output_axis_tready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
length_max = Signal(intbv(0)[16:])
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_hdr_valid = Signal(bool(0))
output_axis_hdr_pad = Signal(bool(0))
output_axis_hdr_truncate = Signal(bool(0))
output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
hdr_sink_queue = Queue()
hdr_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
hdr_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=(output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length),
tvalid=output_axis_hdr_valid,
tready=output_axis_hdr_ready,
fifo=hdr_sink_queue,
pause=hdr_sink_pause,
name='hdr_sink')
# DUT
dut = dut_axis_frame_length_adjust_fifo_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_valid,
output_axis_hdr_ready,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
length_min,
length_max)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while input_axis_tvalid or output_axis_tvalid:
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
length_min.next = 1
length_max.next = 20
for lmax in range(1,18):
for lmin in range(0,lmax+1):
length_min.next = lmin
length_max.next = lmax
for payload_len in range(1,18):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1.user = 1
for wait in wait_normal,:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
hdr = hdr_sink_queue.get(False)
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink_queue.empty()
assert hdr_sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, hdr_sink, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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tb/test_axis_frame_length_adjust_fifo_64.v Normal file
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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_length_adjust_fifo_64;
// parameters
localparam DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
localparam FRAME_FIFO_ADDR_WIDTH = 9;
localparam HEADER_FIFO_ADDR_WIDTH = 3;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_hdr_ready = 0;
reg output_axis_tready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire output_axis_hdr_valid;
wire output_axis_hdr_pad;
wire output_axis_hdr_truncate;
wire [15:0] output_axis_hdr_length;
wire [15:0] output_axis_hdr_original_length;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
length_min,
length_max);
$to_myhdl(input_axis_tready,
output_axis_hdr_valid,
output_axis_hdr_pad,
output_axis_hdr_truncate,
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_frame_length_adjust_fifo_64.lxt");
$dumpvars(0, test_axis_frame_length_adjust_fifo_64);
end
axis_frame_length_adjust_fifo_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_hdr_valid(output_axis_hdr_valid),
.output_axis_hdr_ready(output_axis_hdr_ready),
.output_axis_hdr_pad(output_axis_hdr_pad),
.output_axis_hdr_truncate(output_axis_hdr_truncate),
.output_axis_hdr_length(output_axis_hdr_length),
.output_axis_hdr_original_length(output_axis_hdr_original_length),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule