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https://github.com/alexforencich/verilog-ethernet.git
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Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@ -454,13 +454,13 @@ always @(posedge clk) begin
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adder_b_reg <= -NS_PER_S;
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adder_b_reg <= -NS_PER_S;
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adder_cin_reg <= 0;
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adder_cin_reg <= 0;
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if (ts_tod_ns_reg[29]) begin
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if (ts_tod_ns_reg[29:27] == 3'b111) begin
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// latter half of second; compute offset for next second
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// latter portion of second; compute offset for next second
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adder_b_reg <= -NS_PER_S;
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adder_b_reg <= -NS_PER_S;
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update_state_reg <= 12;
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update_state_reg <= 12;
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adder_busy_reg <= 1'b1;
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adder_busy_reg <= 1'b1;
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end else begin
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end else begin
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// former half of second; compute offset for previous second
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// former portion of second; compute offset for previous second
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adder_b_reg <= NS_PER_S;
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adder_b_reg <= NS_PER_S;
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update_state_reg <= 14;
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update_state_reg <= 14;
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adder_busy_reg <= 1'b1;
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adder_busy_reg <= 1'b1;
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@ -255,12 +255,12 @@ class PtpTdSource(Reset):
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self.ts_tod_offset_ns = (self.ts_tod_ns - self.ts_rel_ns) & 0xffffffff
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self.ts_tod_offset_ns = (self.ts_tod_ns - self.ts_rel_ns) & 0xffffffff
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# compute alternate offset
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# compute alternate offset
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if self.ts_tod_ns & (1 << 29):
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if self.ts_tod_ns >> 27 == 7:
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# latter half of second; compute offset for next second
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# latter portion of second; compute offset for next second
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self.ts_tod_alt_s = self.ts_tod_s+1
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self.ts_tod_alt_s = self.ts_tod_s+1
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self.ts_tod_alt_offset_ns = (self.ts_tod_offset_ns - 1000000000) & 0xffffffff
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self.ts_tod_alt_offset_ns = (self.ts_tod_offset_ns - 1000000000) & 0xffffffff
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else:
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else:
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# former half of second; compute offset for previous second
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# former portion of second; compute offset for previous second
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self.ts_tod_alt_s = self.ts_tod_s-1
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self.ts_tod_alt_s = self.ts_tod_s-1
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self.ts_tod_alt_offset_ns = (self.ts_tod_offset_ns + 1000000000) & 0xffffffff
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self.ts_tod_alt_offset_ns = (self.ts_tod_offset_ns + 1000000000) & 0xffffffff
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