From c65161e696c70f0cf44fa341b6779f43b9df581f Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 17 Feb 2023 16:04:16 -0800 Subject: [PATCH] Remove recursively-expanded macros for module parameters in makefiles Signed-off-by: Alex Forencich --- .../520N_MX/fpga_10g/tb/fpga_core/Makefile | 2 +- .../fpga_10g/tb/fpga_core/Makefile | 2 +- .../fpga_25g/tb/fpga_core/Makefile | 2 +- example/ATLYS/fpga/tb/fpga_core/Makefile | 2 +- example/AU200/fpga_10g/tb/fpga_core/Makefile | 2 +- example/AU250/fpga_10g/tb/fpga_core/Makefile | 2 +- example/AU280/fpga_10g/tb/fpga_core/Makefile | 2 +- example/AU50/fpga_10g/tb/fpga_core/Makefile | 2 +- example/Arty/fpga/tb/fpga_core/Makefile | 2 +- example/C10LP/fpga/tb/fpga_core/Makefile | 2 +- example/DE2-115/fpga/tb/fpga_core/Makefile | 2 +- example/DE5-Net/fpga/tb/fpga_core/Makefile | 2 +- example/ExaNIC_X10/fpga/tb/fpga_core/Makefile | 2 +- .../ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile | 2 +- .../HTG9200/fpga_10g/tb/fpga_core/Makefile | 2 +- example/HXT100G/fpga/tb/fpga_core/Makefile | 2 +- .../HXT100G/fpga_cxpt16/tb/fpga_core/Makefile | 2 +- example/KC705/fpga_gmii/tb/fpga_core/Makefile | 2 +- .../KC705/fpga_rgmii/tb/fpga_core/Makefile | 2 +- .../KC705/fpga_sgmii/tb/fpga_core/Makefile | 2 +- example/ML605/fpga_gmii/tb/fpga_core/Makefile | 2 +- .../ML605/fpga_rgmii/tb/fpga_core/Makefile | 2 +- .../ML605/fpga_sgmii/tb/fpga_core/Makefile | 2 +- .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 2 +- example/NexysVideo/fpga/tb/fpga_core/Makefile | 2 +- example/RV901T/fpga/tb/fpga_core/Makefile | 2 +- .../S10MX_DK/fpga_10g/tb/fpga_core/Makefile | 2 +- example/VCU108/fpga_10g/tb/fpga_core/Makefile | 2 +- example/VCU108/fpga_1g/tb/fpga_core/Makefile | 2 +- example/VCU118/fpga_10g/tb/fpga_core/Makefile | 2 +- example/VCU118/fpga_1g/tb/fpga_core/Makefile | 2 +- example/VCU118/fpga_25g/tb/fpga_core/Makefile | 2 +- .../VCU1525/fpga_10g/tb/fpga_core/Makefile | 2 +- example/ZCU102/fpga/tb/fpga_core/Makefile | 2 +- example/ZCU106/fpga/tb/fpga_core/Makefile | 2 +- example/fb2CG/fpga_10g/tb/fpga_core/Makefile | 2 +- tb/arp/Makefile | 14 ++-- tb/arp_cache/Makefile | 2 +- tb/arp_eth_rx/Makefile | 6 +- tb/arp_eth_tx/Makefile | 6 +- tb/axis_baser_rx_64/Makefile | 12 +-- tb/axis_baser_tx_64/Makefile | 22 +++--- tb/axis_gmii_rx/Makefile | 10 +-- tb/axis_gmii_tx/Makefile | 18 ++--- tb/axis_xgmii_rx_32/Makefile | 12 +-- tb/axis_xgmii_rx_64/Makefile | 12 +-- tb/axis_xgmii_tx_32/Makefile | 22 +++--- tb/axis_xgmii_tx_64/Makefile | 22 +++--- tb/eth_axis_rx/Makefile | 6 +- tb/eth_axis_tx/Makefile | 6 +- tb/eth_mac_10g/Makefile | 32 ++++---- tb/eth_mac_10g_fifo/Makefile | 62 +++++++-------- tb/eth_mac_1g/Makefile | 26 +++---- tb/eth_mac_1g_fifo/Makefile | 30 +++---- tb/eth_mac_1g_gmii/Makefile | 4 +- tb/eth_mac_1g_gmii_fifo/Makefile | 30 +++---- tb/eth_mac_1g_rgmii/Makefile | 4 +- tb/eth_mac_1g_rgmii_fifo/Makefile | 30 +++---- tb/eth_mac_mii/Makefile | 4 +- tb/eth_mac_mii_fifo/Makefile | 30 +++---- tb/eth_mac_phy_10g/Makefile | 48 ++++++------ tb/eth_mac_phy_10g_fifo/Makefile | 78 +++++++++---------- tb/eth_phy_10g/Makefile | 22 +++--- tb/ptp_clock/Makefile | 22 +++--- tb/ptp_clock_cdc/Makefile | 12 +-- tb/ptp_perout/Makefile | 20 ++--- tb/xgmii_baser_dec_64/Makefile | 6 +- tb/xgmii_baser_enc_64/Makefile | 6 +- 68 files changed, 354 insertions(+), 354 deletions(-) diff --git a/example/520N_MX/fpga_10g/tb/fpga_core/Makefile b/example/520N_MX/fpga_10g/tb/fpga_core/Makefile index 8541e6ca..36af9e16 100644 --- a/example/520N_MX/fpga_10g/tb/fpga_core/Makefile +++ b/example/520N_MX/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile b/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile +++ b/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ATLYS/fpga/tb/fpga_core/Makefile b/example/ATLYS/fpga/tb/fpga_core/Makefile index 5f583808..6a09f412 100644 --- a/example/ATLYS/fpga/tb/fpga_core/Makefile +++ b/example/ATLYS/fpga/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU200/fpga_10g/tb/fpga_core/Makefile b/example/AU200/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/AU200/fpga_10g/tb/fpga_core/Makefile +++ b/example/AU200/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU250/fpga_10g/tb/fpga_core/Makefile b/example/AU250/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/AU250/fpga_10g/tb/fpga_core/Makefile +++ b/example/AU250/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU280/fpga_10g/tb/fpga_core/Makefile b/example/AU280/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/AU280/fpga_10g/tb/fpga_core/Makefile +++ b/example/AU280/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/AU50/fpga_10g/tb/fpga_core/Makefile b/example/AU50/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/AU50/fpga_10g/tb/fpga_core/Makefile +++ b/example/AU50/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/Arty/fpga/tb/fpga_core/Makefile b/example/Arty/fpga/tb/fpga_core/Makefile index 1181f3bf..72017d7d 100644 --- a/example/Arty/fpga/tb/fpga_core/Makefile +++ b/example/Arty/fpga/tb/fpga_core/Makefile @@ -62,7 +62,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/C10LP/fpga/tb/fpga_core/Makefile b/example/C10LP/fpga/tb/fpga_core/Makefile index c6328a44..2c0f29ce 100644 --- a/example/C10LP/fpga/tb/fpga_core/Makefile +++ b/example/C10LP/fpga/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/DE2-115/fpga/tb/fpga_core/Makefile b/example/DE2-115/fpga/tb/fpga_core/Makefile index 8c990bc4..c5c8c030 100644 --- a/example/DE2-115/fpga/tb/fpga_core/Makefile +++ b/example/DE2-115/fpga/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/DE5-Net/fpga/tb/fpga_core/Makefile b/example/DE5-Net/fpga/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/DE5-Net/fpga/tb/fpga_core/Makefile +++ b/example/DE5-Net/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile b/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile +++ b/example/ExaNIC_X10/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile b/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile +++ b/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/HTG9200/fpga_10g/tb/fpga_core/Makefile b/example/HTG9200/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/HTG9200/fpga_10g/tb/fpga_core/Makefile +++ b/example/HTG9200/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/HXT100G/fpga/tb/fpga_core/Makefile b/example/HXT100G/fpga/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/HXT100G/fpga/tb/fpga_core/Makefile +++ b/example/HXT100G/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile b/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile index 22a78d71..c0dda222 100644 --- a/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile +++ b/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile @@ -41,7 +41,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_crosspoint.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/KC705/fpga_gmii/tb/fpga_core/Makefile b/example/KC705/fpga_gmii/tb/fpga_core/Makefile index 5f583808..6a09f412 100644 --- a/example/KC705/fpga_gmii/tb/fpga_core/Makefile +++ b/example/KC705/fpga_gmii/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/KC705/fpga_rgmii/tb/fpga_core/Makefile b/example/KC705/fpga_rgmii/tb/fpga_core/Makefile index c6328a44..2c0f29ce 100644 --- a/example/KC705/fpga_rgmii/tb/fpga_core/Makefile +++ b/example/KC705/fpga_rgmii/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/KC705/fpga_sgmii/tb/fpga_core/Makefile b/example/KC705/fpga_sgmii/tb/fpga_core/Makefile index 9c8aced9..8a2c204b 100644 --- a/example/KC705/fpga_sgmii/tb/fpga_core/Makefile +++ b/example/KC705/fpga_sgmii/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ML605/fpga_gmii/tb/fpga_core/Makefile b/example/ML605/fpga_gmii/tb/fpga_core/Makefile index 5f583808..6a09f412 100644 --- a/example/ML605/fpga_gmii/tb/fpga_core/Makefile +++ b/example/ML605/fpga_gmii/tb/fpga_core/Makefile @@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ML605/fpga_rgmii/tb/fpga_core/Makefile b/example/ML605/fpga_rgmii/tb/fpga_core/Makefile index c6328a44..2c0f29ce 100644 --- a/example/ML605/fpga_rgmii/tb/fpga_core/Makefile +++ b/example/ML605/fpga_rgmii/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ML605/fpga_sgmii/tb/fpga_core/Makefile b/example/ML605/fpga_sgmii/tb/fpga_core/Makefile index 9c8aced9..8a2c204b 100644 --- a/example/ML605/fpga_sgmii/tb/fpga_core/Makefile +++ b/example/ML605/fpga_sgmii/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/NexysVideo/fpga/tb/fpga_core/Makefile b/example/NexysVideo/fpga/tb/fpga_core/Makefile index c6328a44..2c0f29ce 100644 --- a/example/NexysVideo/fpga/tb/fpga_core/Makefile +++ b/example/NexysVideo/fpga/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/RV901T/fpga/tb/fpga_core/Makefile b/example/RV901T/fpga/tb/fpga_core/Makefile index c6328a44..2c0f29ce 100644 --- a/example/RV901T/fpga/tb/fpga_core/Makefile +++ b/example/RV901T/fpga/tb/fpga_core/Makefile @@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile b/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile index 8541e6ca..36af9e16 100644 --- a/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile +++ b/example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU108/fpga_10g/tb/fpga_core/Makefile b/example/VCU108/fpga_10g/tb/fpga_core/Makefile index 7641e3f0..682ed9c2 100644 --- a/example/VCU108/fpga_10g/tb/fpga_core/Makefile +++ b/example/VCU108/fpga_10g/tb/fpga_core/Makefile @@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU108/fpga_1g/tb/fpga_core/Makefile b/example/VCU108/fpga_1g/tb/fpga_core/Makefile index 9c8aced9..8a2c204b 100644 --- a/example/VCU108/fpga_1g/tb/fpga_core/Makefile +++ b/example/VCU108/fpga_1g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU118/fpga_10g/tb/fpga_core/Makefile b/example/VCU118/fpga_10g/tb/fpga_core/Makefile index 7641e3f0..682ed9c2 100644 --- a/example/VCU118/fpga_10g/tb/fpga_core/Makefile +++ b/example/VCU118/fpga_10g/tb/fpga_core/Makefile @@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU118/fpga_1g/tb/fpga_core/Makefile b/example/VCU118/fpga_1g/tb/fpga_core/Makefile index 9c8aced9..8a2c204b 100644 --- a/example/VCU118/fpga_1g/tb/fpga_core/Makefile +++ b/example/VCU118/fpga_1g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU118/fpga_25g/tb/fpga_core/Makefile b/example/VCU118/fpga_25g/tb/fpga_core/Makefile index 7641e3f0..682ed9c2 100644 --- a/example/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/example/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/VCU1525/fpga_10g/tb/fpga_core/Makefile b/example/VCU1525/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/VCU1525/fpga_10g/tb/fpga_core/Makefile +++ b/example/VCU1525/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ZCU102/fpga/tb/fpga_core/Makefile b/example/ZCU102/fpga/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/ZCU102/fpga/tb/fpga_core/Makefile +++ b/example/ZCU102/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/ZCU106/fpga/tb/fpga_core/Makefile b/example/ZCU106/fpga/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/ZCU106/fpga/tb/fpga_core/Makefile +++ b/example/ZCU106/fpga/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/example/fb2CG/fpga_10g/tb/fpga_core/Makefile b/example/fb2CG/fpga_10g/tb/fpga_core/Makefile index 87e6cf66..d840fbe0 100644 --- a/example/fb2CG/fpga_10g/tb/fpga_core/Makefile +++ b/example/fb2CG/fpga_10g/tb/fpga_core/Makefile @@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -#export PARAM_A ?= value +#export PARAM_A := value ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/arp/Makefile b/tb/arp/Makefile index e0e93714..c9b623cf 100644 --- a/tb/arp/Makefile +++ b/tb/arp/Makefile @@ -36,13 +36,13 @@ VERILOG_SOURCES += ../../rtl/arp_cache.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CACHE_ADDR_WIDTH ?= 2 -export PARAM_REQUEST_RETRY_COUNT ?= 4 -export PARAM_REQUEST_RETRY_INTERVAL ?= 300 -export PARAM_REQUEST_TIMEOUT ?= 800 +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CACHE_ADDR_WIDTH := 2 +export PARAM_REQUEST_RETRY_COUNT := 4 +export PARAM_REQUEST_RETRY_INTERVAL := 300 +export PARAM_REQUEST_TIMEOUT := 800 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/arp_cache/Makefile b/tb/arp_cache/Makefile index ccb5334b..12b9df7c 100644 --- a/tb/arp_cache/Makefile +++ b/tb/arp_cache/Makefile @@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_CACHE_ADDR_WIDTH ?= 2 +export PARAM_CACHE_ADDR_WIDTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/arp_eth_rx/Makefile b/tb/arp_eth_rx/Makefile index f8fe08ab..9a46b94d 100644 --- a/tb/arp_eth_rx/Makefile +++ b/tb/arp_eth_rx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/arp_eth_tx/Makefile b/tb/arp_eth_tx/Makefile index fb605e5d..1cce30c4 100644 --- a/tb/arp_eth_tx/Makefile +++ b/tb/arp_eth_tx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_baser_rx_64/Makefile b/tb/axis_baser_rx_64/Makefile index 654a8683..67ece95a 100644 --- a/tb/axis_baser_rx_64/Makefile +++ b/tb/axis_baser_rx_64/Makefile @@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_baser_tx_64/Makefile b/tb/axis_baser_tx_64/Makefile index 76dece3f..26b54659 100644 --- a/tb/axis_baser_tx_64/Makefile +++ b/tb/axis_baser_tx_64/Makefile @@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_gmii_rx/Makefile b/tb/axis_gmii_rx/Makefile index 2a87edb7..1fbe4ebb 100644 --- a/tb/axis_gmii_rx/Makefile +++ b/tb/axis_gmii_rx/Makefile @@ -33,11 +33,11 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_PTP_TS_ENABLE ?= 0 -export PARAM_PTP_TS_WIDTH ?= 96 -#export PARAM_USER_WIDTH ?= (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_PTP_TS_ENABLE := 0 +export PARAM_PTP_TS_WIDTH := 96 +#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_gmii_tx/Makefile b/tb/axis_gmii_tx/Makefile index f97bec4a..a1aebdac 100644 --- a/tb/axis_gmii_tx/Makefile +++ b/tb/axis_gmii_tx/Makefile @@ -33,15 +33,15 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 0 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= PTP_TS_ENABLE -export PARAM_PTP_TAG_WIDTH ?= 16 -#export PARAM_USER_WIDTH ?= (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 -export PARAM_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 0 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := PTP_TS_ENABLE +export PARAM_PTP_TAG_WIDTH := 16 +#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 +export PARAM_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_xgmii_rx_32/Makefile b/tb/axis_xgmii_rx_32/Makefile index 1e978b02..c104ad28 100644 --- a/tb/axis_xgmii_rx_32/Makefile +++ b/tb/axis_xgmii_rx_32/Makefile @@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 32 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 32 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_xgmii_rx_64/Makefile b/tb/axis_xgmii_rx_64/Makefile index 8f0d9b22..923a45d7 100644 --- a/tb/axis_xgmii_rx_64/Makefile +++ b/tb/axis_xgmii_rx_64/Makefile @@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_xgmii_tx_32/Makefile b/tb/axis_xgmii_tx_32/Makefile index 3e0a0c89..e24b2f9a 100644 --- a/tb/axis_xgmii_tx_32/Makefile +++ b/tb/axis_xgmii_tx_32/Makefile @@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 32 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 32 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/axis_xgmii_tx_64/Makefile b/tb/axis_xgmii_tx_64/Makefile index 86797aea..7743dd38 100644 --- a/tb/axis_xgmii_tx_64/Makefile +++ b/tb/axis_xgmii_tx_64/Makefile @@ -33,17 +33,17 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_TS_ENABLE ?= 1 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_PTP_TAG_ENABLE ?= $(PARAM_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_axis_rx/Makefile b/tb/eth_axis_rx/Makefile index e13de525..c10b5427 100644 --- a/tb/eth_axis_rx/Makefile +++ b/tb/eth_axis_rx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_axis_tx/Makefile b/tb/eth_axis_tx/Makefile index e290f7f9..3390142a 100644 --- a/tb/eth_axis_tx/Makefile +++ b/tb/eth_axis_tx/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_10g/Makefile b/tb/eth_mac_10g/Makefile index a09e617c..d9df95bc 100644 --- a/tb/eth_mac_10g/Makefile +++ b/tb/eth_mac_10g/Makefile @@ -37,22 +37,22 @@ VERILOG_SOURCES += ../../rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_TX_PTP_TAG_WIDTH ?= 16 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TAG_WIDTH := 16 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_WIDTH := 96 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_10g_fifo/Makefile b/tb/eth_mac_10g_fifo/Makefile index 18680e33..b7c4c1bf 100644 --- a/tb/eth_mac_10g_fifo/Makefile +++ b/tb/eth_mac_10g_fifo/Makefile @@ -42,37 +42,37 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_AXIS_DATA_WIDTH ?= $(PARAM_DATA_WIDTH) -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 64 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_AXIS_DATA_WIDTH := $(PARAM_DATA_WIDTH) +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FIFO_RAM_PIPELINE := 1 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FIFO_RAM_PIPELINE := 1 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_PTP_USE_SAMPLE_CLOCK := 0 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_FIFO_DEPTH := 64 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_1g/Makefile b/tb/eth_mac_1g/Makefile index 5d88a876..3c8e9186 100644 --- a/tb/eth_mac_1g/Makefile +++ b/tb/eth_mac_1g/Makefile @@ -35,19 +35,19 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 8 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_PTP_TS_ENABLE ?= 0 -export PARAM_TX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_TX_PTP_TAG_WIDTH ?= 16 -export PARAM_RX_PTP_TS_ENABLE ?= 0 -export PARAM_RX_PTP_TS_WIDTH ?= 96 -# export PARAM_TX_USER_WIDTH ?= (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1 -export PARAM_TX_USER_WIDTH ?= 1 -# export PARAM_RX_USER_WIDTH ?= (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1 -export PARAM_RX_USER_WIDTH ?= 1 +export PARAM_DATA_WIDTH := 8 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_PTP_TS_ENABLE := 0 +export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TAG_WIDTH := 16 +export PARAM_RX_PTP_TS_ENABLE := 0 +export PARAM_RX_PTP_TS_WIDTH := 96 +# export PARAM_TX_USER_WIDTH := (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1 +export PARAM_TX_USER_WIDTH := 1 +# export PARAM_RX_USER_WIDTH := (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1 +export PARAM_RX_USER_WIDTH := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_1g_fifo/Makefile b/tb/eth_mac_1g_fifo/Makefile index c84ed34e..f4fef6d8 100644 --- a/tb/eth_mac_1g_fifo/Makefile +++ b/tb/eth_mac_1g_fifo/Makefile @@ -39,21 +39,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_1g_gmii/Makefile b/tb/eth_mac_1g_gmii/Makefile index b8cbfe8e..572a4f42 100644 --- a/tb/eth_mac_1g_gmii/Makefile +++ b/tb/eth_mac_1g_gmii/Makefile @@ -40,8 +40,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_1g_gmii_fifo/Makefile b/tb/eth_mac_1g_gmii_fifo/Makefile index 2494ee7c..1af7ce2d 100644 --- a/tb/eth_mac_1g_gmii_fifo/Makefile +++ b/tb/eth_mac_1g_gmii_fifo/Makefile @@ -44,21 +44,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_1g_rgmii/Makefile b/tb/eth_mac_1g_rgmii/Makefile index 5fc298f0..752a44a7 100644 --- a/tb/eth_mac_1g_rgmii/Makefile +++ b/tb/eth_mac_1g_rgmii/Makefile @@ -40,8 +40,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_1g_rgmii_fifo/Makefile b/tb/eth_mac_1g_rgmii_fifo/Makefile index 7c63de48..45a3c981 100644 --- a/tb/eth_mac_1g_rgmii_fifo/Makefile +++ b/tb/eth_mac_1g_rgmii_fifo/Makefile @@ -44,21 +44,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_mii/Makefile b/tb/eth_mac_mii/Makefile index d24b6047..e2d0ded7 100644 --- a/tb/eth_mac_mii/Makefile +++ b/tb/eth_mac_mii/Makefile @@ -38,8 +38,8 @@ VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_mii_fifo/Makefile b/tb/eth_mac_mii_fifo/Makefile index 8f54d651..ce44ec56 100644 --- a/tb/eth_mac_mii_fifo/Makefile +++ b/tb/eth_mac_mii_fifo/Makefile @@ -42,21 +42,21 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_AXIS_DATA_WIDTH ?= 8 -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_AXIS_DATA_WIDTH := 8 +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_phy_10g/Makefile b/tb/eth_mac_phy_10g/Makefile index 161b0f7d..a6747924 100644 --- a/tb/eth_mac_phy_10g/Makefile +++ b/tb/eth_mac_phy_10g/Makefile @@ -42,30 +42,30 @@ VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_TX_PTP_TAG_WIDTH ?= 16 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_WIDTH ?= 96 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) -export PARAM_BIT_REVERSE ?= 0 -export PARAM_SCRAMBLER_DISABLE ?= 0 -export PARAM_PRBS31_ENABLE ?= 1 -export PARAM_TX_SERDES_PIPELINE ?= 2 -export PARAM_RX_SERDES_PIPELINE ?= 2 -export PARAM_BITSLIP_HIGH_CYCLES ?= 1 -export PARAM_BITSLIP_LOW_CYCLES ?= 8 -export PARAM_COUNT_125US ?= 195 +export PARAM_DATA_WIDTH := 64 +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TAG_WIDTH := 16 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_WIDTH := 96 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) +export PARAM_BIT_REVERSE := 0 +export PARAM_SCRAMBLER_DISABLE := 0 +export PARAM_PRBS31_ENABLE := 1 +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 1 +export PARAM_BITSLIP_LOW_CYCLES := 8 +export PARAM_COUNT_125US := 195 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_phy_10g_fifo/Makefile b/tb/eth_mac_phy_10g_fifo/Makefile index 9da48b43..c74477c6 100644 --- a/tb/eth_mac_phy_10g_fifo/Makefile +++ b/tb/eth_mac_phy_10g_fifo/Makefile @@ -47,45 +47,45 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_HDR_WIDTH ?= 2 -export PARAM_AXIS_DATA_WIDTH ?= $(PARAM_DATA_WIDTH) -export PARAM_AXIS_KEEP_ENABLE ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) -export PARAM_AXIS_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) -export PARAM_ENABLE_PADDING ?= 1 -export PARAM_ENABLE_DIC ?= 1 -export PARAM_MIN_FRAME_LENGTH ?= 64 -export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_TX_FRAME_FIFO ?= 1 -export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) -export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) -export PARAM_TX_DROP_WHEN_FULL ?= 0 -export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FIFO_RAM_PIPELINE ?= 1 -export PARAM_RX_FRAME_FIFO ?= 1 -export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) -export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_RX_DROP_WHEN_FULL ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_PTP_PERIOD_NS ?= 6 -export PARAM_PTP_PERIOD_FNS ?= 26214 -export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0 -export PARAM_TX_PTP_TS_ENABLE ?= 1 -export PARAM_RX_PTP_TS_ENABLE ?= 1 -export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 64 -export PARAM_PTP_TS_WIDTH ?= 96 -export PARAM_TX_PTP_TAG_ENABLE ?= $(PARAM_TX_PTP_TS_ENABLE) -export PARAM_PTP_TAG_WIDTH ?= 16 -export PARAM_TX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) -export PARAM_RX_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) -export PARAM_BIT_REVERSE ?= 0 -export PARAM_SCRAMBLER_DISABLE ?= 0 -export PARAM_PRBS31_ENABLE ?= 1 -export PARAM_TX_SERDES_PIPELINE ?= 2 -export PARAM_RX_SERDES_PIPELINE ?= 2 -export PARAM_BITSLIP_HIGH_CYCLES ?= 1 -export PARAM_BITSLIP_LOW_CYCLES ?= 8 -export PARAM_COUNT_125US ?= 195 +export PARAM_DATA_WIDTH := 64 +export PARAM_HDR_WIDTH := 2 +export PARAM_AXIS_DATA_WIDTH := $(PARAM_DATA_WIDTH) +export PARAM_AXIS_KEEP_ENABLE := $(shell expr $(PARAM_AXIS_DATA_WIDTH) \> 8 ) +export PARAM_AXIS_KEEP_WIDTH := $(shell expr $(PARAM_AXIS_DATA_WIDTH) / 8 ) +export PARAM_ENABLE_PADDING := 1 +export PARAM_ENABLE_DIC := 1 +export PARAM_MIN_FRAME_LENGTH := 64 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FIFO_RAM_PIPELINE := 1 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FIFO_RAM_PIPELINE := 1 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_PTP_PERIOD_NS := 6 +export PARAM_PTP_PERIOD_FNS := 26214 +export PARAM_PTP_USE_SAMPLE_CLOCK := 0 +export PARAM_TX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_TX_PTP_TS_FIFO_DEPTH := 64 +export PARAM_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_PTP_TAG_WIDTH := 16 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) +export PARAM_BIT_REVERSE := 0 +export PARAM_SCRAMBLER_DISABLE := 0 +export PARAM_PRBS31_ENABLE := 1 +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 1 +export PARAM_BITSLIP_LOW_CYCLES := 8 +export PARAM_COUNT_125US := 195 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_phy_10g/Makefile b/tb/eth_phy_10g/Makefile index 3ef85474..dbcfeec7 100644 --- a/tb/eth_phy_10g/Makefile +++ b/tb/eth_phy_10g/Makefile @@ -43,17 +43,17 @@ VERILOG_SOURCES += ../../rtl/xgmii_baser_enc_64.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 -export PARAM_BIT_REVERSE ?= 0 -export PARAM_SCRAMBLER_DISABLE ?= 0 -export PARAM_PRBS31_ENABLE ?= 1 -export PARAM_TX_SERDES_PIPELINE ?= 2 -export PARAM_RX_SERDES_PIPELINE ?= 2 -export PARAM_BITSLIP_HIGH_CYCLES ?= 1 -export PARAM_BITSLIP_LOW_CYCLES ?= 8 -export PARAM_COUNT_125US ?= 195 +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 +export PARAM_BIT_REVERSE := 0 +export PARAM_SCRAMBLER_DISABLE := 0 +export PARAM_PRBS31_ENABLE := 1 +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 1 +export PARAM_BITSLIP_LOW_CYCLES := 8 +export PARAM_COUNT_125US := 195 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/ptp_clock/Makefile b/tb/ptp_clock/Makefile index 5adaf22e..972cfc36 100644 --- a/tb/ptp_clock/Makefile +++ b/tb/ptp_clock/Makefile @@ -32,17 +32,17 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_PERIOD_NS_WIDTH ?= 4 -export PARAM_OFFSET_NS_WIDTH ?= 4 -export PARAM_DRIFT_NS_WIDTH ?= 4 -export PARAM_FNS_WIDTH ?= 16 -export PARAM_PERIOD_NS ?= 6 -export PARAM_PERIOD_FNS ?= 26214 -export PARAM_DRIFT_ENABLE ?= 1 -export PARAM_DRIFT_NS ?= 0 -export PARAM_DRIFT_FNS ?= 2 -export PARAM_DRIFT_RATE ?= 5 -export PARAM_PIPELINE_OUTPUT ?= 0 +export PARAM_PERIOD_NS_WIDTH := 4 +export PARAM_OFFSET_NS_WIDTH := 4 +export PARAM_DRIFT_NS_WIDTH := 4 +export PARAM_FNS_WIDTH := 16 +export PARAM_PERIOD_NS := 6 +export PARAM_PERIOD_FNS := 26214 +export PARAM_DRIFT_ENABLE := 1 +export PARAM_DRIFT_NS := 0 +export PARAM_DRIFT_FNS := 2 +export PARAM_DRIFT_RATE := 5 +export PARAM_PIPELINE_OUTPUT := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/ptp_clock_cdc/Makefile b/tb/ptp_clock_cdc/Makefile index 62b4d3d0..2272408e 100644 --- a/tb/ptp_clock_cdc/Makefile +++ b/tb/ptp_clock_cdc/Makefile @@ -32,12 +32,12 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_TS_WIDTH ?= 96 -export PARAM_NS_WIDTH ?= 4 -export PARAM_FNS_WIDTH ?= 16 -export PARAM_USE_SAMPLE_CLOCK ?= 1 -export PARAM_LOG_RATE ?= 3 -export PARAM_PIPELINE_OUTPUT ?= 0 +export PARAM_TS_WIDTH := 96 +export PARAM_NS_WIDTH := 4 +export PARAM_FNS_WIDTH := 16 +export PARAM_USE_SAMPLE_CLOCK := 1 +export PARAM_LOG_RATE := 3 +export PARAM_PIPELINE_OUTPUT := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/ptp_perout/Makefile b/tb/ptp_perout/Makefile index 08536e37..2f3cb72a 100644 --- a/tb/ptp_perout/Makefile +++ b/tb/ptp_perout/Makefile @@ -32,16 +32,16 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_FNS_ENABLE ?= 1 -export PARAM_OUT_START_S ?= 0 -export PARAM_OUT_START_NS ?= 0 -export PARAM_OUT_START_FNS ?= 0 -export PARAM_OUT_PERIOD_S ?= 1 -export PARAM_OUT_PERIOD_NS ?= 0 -export PARAM_OUT_PERIOD_FNS ?= 0 -export PARAM_OUT_WIDTH_S ?= 0 -export PARAM_OUT_WIDTH_NS ?= 1000 -export PARAM_OUT_WIDTH_FNS ?= 0 +export PARAM_FNS_ENABLE := 1 +export PARAM_OUT_START_S := 0 +export PARAM_OUT_START_NS := 0 +export PARAM_OUT_START_FNS := 0 +export PARAM_OUT_PERIOD_S := 1 +export PARAM_OUT_PERIOD_NS := 0 +export PARAM_OUT_PERIOD_FNS := 0 +export PARAM_OUT_WIDTH_S := 0 +export PARAM_OUT_WIDTH_NS := 1000 +export PARAM_OUT_WIDTH_FNS := 0 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/xgmii_baser_dec_64/Makefile b/tb/xgmii_baser_dec_64/Makefile index 8e023a76..dd3de46b 100644 --- a/tb/xgmii_baser_dec_64/Makefile +++ b/tb/xgmii_baser_dec_64/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/xgmii_baser_enc_64/Makefile b/tb/xgmii_baser_enc_64/Makefile index 57bf5ec2..d65eb210 100644 --- a/tb/xgmii_baser_enc_64/Makefile +++ b/tb/xgmii_baser_enc_64/Makefile @@ -32,9 +32,9 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DATA_WIDTH ?= 64 -export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) -export PARAM_HDR_WIDTH ?= 2 +export PARAM_DATA_WIDTH := 64 +export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_HDR_WIDTH := 2 ifeq ($(SIM), icarus) PLUSARGS += -fst