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Simplify logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-07-24 16:08:34 -07:00
parent 2601127679
commit c7f3b4632b
3 changed files with 15 additions and 5 deletions
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8
rtl/axis_baser_rx_64.v
View File

@ -340,13 +340,18 @@ always @* begin
m_axis_tlast_next = 1'b0;
m_axis_tuser_next[0] = 1'b0;
if (input_type_d0[3]) begin
// INPUT_TYPE_TERM_*
reset_crc = 1'b1;
update_crc_last = 1'b1;
end
if (input_type_d0 == INPUT_TYPE_DATA) begin
state_next = STATE_PAYLOAD;
end else if (input_type_d0[3]) begin
// INPUT_TYPE_TERM_*
if (input_type_d0 <= INPUT_TYPE_TERM_4) begin
// end this cycle
reset_crc = 1'b1;
case (input_type_d0)
INPUT_TYPE_TERM_0: m_axis_tkeep_next = 8'b00001111;
INPUT_TYPE_TERM_1: m_axis_tkeep_next = 8'b00011111;
@ -369,7 +374,6 @@ always @* begin
state_next = STATE_IDLE;
end else begin
// need extra cycle
update_crc_last = 1'b1;
state_next = STATE_LAST;
end
end else begin

5
rtl/axis_xgmii_rx_32.v
View File

@ -319,6 +319,10 @@ always @* begin
last_cycle_tkeep_next = tkeep_mask;
if (detect_term) begin
reset_crc = 1'b1;
end
if (control_masked) begin
// control or error characters in packet
m_axis_tlast_next = 1'b1;
@ -329,7 +333,6 @@ always @* begin
end else if (detect_term) begin
if (detect_term[0]) begin
// end this cycle
reset_crc = 1'b1;
m_axis_tkeep_next = 4'b1111;
m_axis_tlast_next = 1'b1;
if (detect_term[0] && crc_valid3_save) begin

7
rtl/axis_xgmii_rx_64.v
View File

@ -353,6 +353,11 @@ always @* begin
last_cycle_tkeep_next = {4'b0000, tkeep_mask[7:4]};
if (detect_term) begin
reset_crc = 1'b1;
update_crc_last = 1'b1;
end
if (control_masked) begin
// control or error characters in packet
m_axis_tlast_next = 1'b1;
@ -363,7 +368,6 @@ always @* begin
end else if (detect_term) begin
if (detect_term[4:0]) begin
// end this cycle
reset_crc = 1'b1;
m_axis_tkeep_next = {tkeep_mask[3:0], 4'b1111};
m_axis_tlast_next = 1'b1;
if ((detect_term[0] && crc_valid7_save) ||
@ -380,7 +384,6 @@ always @* begin
state_next = STATE_IDLE;
end else begin
// need extra cycle
update_crc_last = 1'b1;
state_next = STATE_LAST;
end
end else begin