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Add generic LFSR module
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Alex Forencich
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rtl/lfsr.v
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346
rtl/lfsr.v
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/*
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Copyright (c) 2016 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Parametrizable combinatorial parallel LFSR/CRC
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*/
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module lfsr #
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(
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// width of LFSR
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parameter LFSR_WIDTH = 31,
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// LFSR polynomial
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parameter LFSR_POLY = 31'h10000001,
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// LFSR configuration: "GALOIS", "FIBONACCI"
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parameter LFSR_CONFIG = "FIBONACCI",
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// bit-reverse input and output
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parameter REVERSE = 0,
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// width of data input
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parameter DATA_WIDTH = 8,
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// width of CRC/LFSR output
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parameter OUTPUT_WIDTH = LFSR_WIDTH,
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// implementation style: "AUTO", "LOOP", "REDUCTION"
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parameter STYLE = "AUTO"
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)
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(
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [LFSR_WIDTH-1:0] lfsr_in,
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output wire [OUTPUT_WIDTH-1:0] lfsr_out
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);
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/*
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Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR
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next state computation, shifting DATA_WIDTH bits per pass through the module. Input data
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is XORed with LFSR feedback path, tie data_in to zero if this is not required.
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Works in two parts: statically computes a set of bit masks, then uses these bit masks to
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select bits for XORing to compute the next state.
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Ports:
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data_in
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Data bits to be XORed with the LFSR feedback path (DATA_WIDTH bits)
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lfsr_in
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LFSR/CRC current state input (LFSR_WIDTH bits)
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lfsr_out
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LFSR/CRC next state output (OUTPUT_WIDTH bits)
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Parameters:
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LFSR_WIDTH
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Specify width of LFSR/CRC register
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LFSR_POLY
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Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
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x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
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would be represented as
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32'h04c11db7
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Note that the largest term (x^32) is suppressed. This term is generated automatically based
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on LFSR_WIDTH.
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LFSR_CONFIG
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Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
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for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
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scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
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generators and checkers.
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Fibonacci style (example for 64b66b scrambler, 0x8000000001)
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,-----------------------------(+)<------------------------------,
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| ^ |
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| .----. .----. .----. | .----. .----. .----. |
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`->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |->(+)<-DIN (MSB first)
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'----' '----' '----' '----' '----' '----'
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Galois style (example for CRC16, 0x8005)
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,-------------------+---------------------------------+------------,
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| | | |
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| .----. .----. V .----. .----. .----. V .----. |
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`->| 0 |->| 1 |->(+)->| 2 |->| 3 |->...->| 14 |->(+)->| 15 |->(+)<-DIN (MSB first)
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'----' '----' '----' '----' '----' '----'
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REVERSE
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Bit-reverse LFSR input and output.
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DATA_WIDTH
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Specify width of input data bus. The module will perform one shift per input data bit,
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so if the input data bus is not required tie data_in to zero and set DATA_WIDTH to the
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required number of shifts per clock cycle.
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OUTPUT_WIDTH
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Specify width of output data bus. Defaults to LFSR_WIDTH. Mainly useful for extending
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the output width for LFSRs. Ensure that lfsr_out is properly shifted and truncated so
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that feeding it back around to lfsr_in produces the expected result. Note that if
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OUTPUT_WIDTH is smaller than LFSR_WIDTH, it may not be possible to get the LFSR to
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feed back correctly.
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STYLE
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Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
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is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
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directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
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and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
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reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
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operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
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Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
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problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
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will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
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synthesis translate directives.
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Settings for common LFSR/CRC implementations:
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Name Configuration Length Polynomial Initial value Notes
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CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
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PRBS6 Fibonacci 6 6'h21 any
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PRBS7 Fibonacci 7 7'h41 amy
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PRBS9 Fibonacci 9 9'h021 any ITU V.52
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PRBS10 Fibonacci 10 10'h081 any ITU
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PRBS11 Fibonacci 11 11'h201 any ITU O.152
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PRBS15 Fibonacci 15 15'h4001 any ITU O.152
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PRBS17 Fibonacci 17 17'h04001 any
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PRBS20 Fibonacci 20 20'h00009 any ITU V.57
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PRBS23 Fibonacci 23 23'h040001 any ITU O.151
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PRBS31 Fibonacci 31 31'h10000001 any
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64b66b Fibonacci 58 58'h8000000001 any 10G Ethernet
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128b130b Fibonacci 23 23'h210125 any PCIe gen 3
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*/
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// STATE_WIDTH is OUTPUT_WIDTH or LFSR_WIDTH, whichever is larger
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parameter STATE_WIDTH = OUTPUT_WIDTH > LFSR_WIDTH ? OUTPUT_WIDTH : LFSR_WIDTH;
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reg [LFSR_WIDTH-1:0] lfsr_mask_state[STATE_WIDTH-1:0];
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reg [DATA_WIDTH-1:0] lfsr_mask_data[STATE_WIDTH-1:0];
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reg [LFSR_WIDTH-1:0] state_val = 0;
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reg [DATA_WIDTH-1:0] data_val = 0;
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integer i, j, k;
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initial begin
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// init bit masks
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for (i = 0; i < STATE_WIDTH; i = i + 1) begin
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lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}};
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if (i < LFSR_WIDTH) begin
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lfsr_mask_state[i][i] = 1'b1;
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end
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lfsr_mask_data[i] = {DATA_WIDTH{1'b0}};
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end
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// simulate shift register
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if (LFSR_CONFIG == "FIBONACCI") begin
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// Fibonacci configuration
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for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
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// determine shift in value
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// current value in last FF, XOR with input data bit (MSB first)
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state_val = lfsr_mask_state[LFSR_WIDTH-1];
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data_val = lfsr_mask_data[LFSR_WIDTH-1];
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data_val = data_val ^ (1 << i);
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// add XOR inputs from correct indicies
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for (j = 1; j < STATE_WIDTH; j = j + 1) begin
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if (LFSR_POLY & (1 << j)) begin
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state_val = lfsr_mask_state[j-1] ^ state_val;
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data_val = lfsr_mask_data[j-1] ^ data_val;
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end
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end
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// shift
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for (j = STATE_WIDTH-1; j > 0; j = j - 1) begin
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lfsr_mask_state[j] = lfsr_mask_state[j-1];
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lfsr_mask_data[j] = lfsr_mask_data[j-1];
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end
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lfsr_mask_state[0] = state_val;
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lfsr_mask_data[0] = data_val;
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end
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end else if (LFSR_CONFIG == "GALOIS") begin
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// Galois configuration
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for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
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// determine shift in value
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// current value in last FF, XOR with input data bit (MSB first)
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state_val = lfsr_mask_state[LFSR_WIDTH-1];
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data_val = lfsr_mask_data[LFSR_WIDTH-1];
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data_val = data_val ^ (1 << i);
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// shift
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for (j = STATE_WIDTH-1; j > 0; j = j - 1) begin
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lfsr_mask_state[j] = lfsr_mask_state[j-1];
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lfsr_mask_data[j] = lfsr_mask_data[j-1];
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end
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lfsr_mask_state[0] = state_val;
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lfsr_mask_data[0] = data_val;
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// add XOR inputs at correct indicies
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for (j = 1; j < STATE_WIDTH; j = j + 1) begin
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if (LFSR_POLY & (1 << j)) begin
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lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
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lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
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end
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end
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end
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end else begin
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$error("Error: unknown configuration setting!");
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$finish;
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end
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// reverse bits if selected
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if (REVERSE) begin
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// reverse order
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for (i = 0; i < OUTPUT_WIDTH/2; i = i + 1) begin
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state_val = lfsr_mask_state[i];
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data_val = lfsr_mask_data[i];
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lfsr_mask_state[i] = lfsr_mask_state[OUTPUT_WIDTH-i-1];
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lfsr_mask_data[i] = lfsr_mask_data[OUTPUT_WIDTH-i-1];
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lfsr_mask_state[OUTPUT_WIDTH-i-1] = state_val;
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lfsr_mask_data[OUTPUT_WIDTH-i-1] = data_val;
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end
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// reverse bits
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for (i = 0; i < OUTPUT_WIDTH; i = i + 1) begin
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state_val = 0;
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for (j = 0; j < STATE_WIDTH; j = j + 1) begin
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state_val[j] = lfsr_mask_state[i][STATE_WIDTH-j-1];
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end
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lfsr_mask_state[i] = state_val;
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data_val = 0;
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for (j = 0; j < DATA_WIDTH; j = j + 1) begin
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data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
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end
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lfsr_mask_data[i] = data_val;
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end
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end
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// for (i = 0; i < OUTPUT_WIDTH; i = i + 1) begin
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// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]);
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// end
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end
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// synthesis translate_off
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`define SIMULATION
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// synthesis translate_on
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`ifdef SIMULATION
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// "AUTO" style is "REDUCTION" for faster simulation
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parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
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`else
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// "AUTO" style is "LOOP" for better synthesis result
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parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
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`endif
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genvar n;
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generate
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if (STYLE_INT == "REDUCTION") begin
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// use Verilog reduction operator
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// fast in iverilog
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// significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer)
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// slightly smaller than generated code with Quartus
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// --> better for simulation
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for (n = 0; n < OUTPUT_WIDTH; n = n + 1) begin : loop
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assign lfsr_out[n] = ^{(lfsr_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
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end
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end else if (STYLE_INT == "LOOP") begin
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// use nested loops
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// very slow in iverilog
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// slightly smaller than generated code with ISE
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// same size as generated code with Quartus
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// --> better for synthesis
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reg [OUTPUT_WIDTH-1:0] lfsr_out_reg = 0;
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assign lfsr_out = lfsr_out_reg;
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always @* begin
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for (i = 0; i < OUTPUT_WIDTH; i = i + 1) begin
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lfsr_out_reg[i] = 0;
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for (j = 0; j < STATE_WIDTH; j = j + 1) begin
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if (lfsr_mask_state[i][j]) begin
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lfsr_out_reg[i] = lfsr_out_reg[i] ^ lfsr_in[j];
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end
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end
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for (j = 0; j < DATA_WIDTH; j = j + 1) begin
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if (lfsr_mask_data[i][j]) begin
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lfsr_out_reg[i] = lfsr_out_reg[i] ^ data_in[j];
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end
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end
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end
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end
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end else begin
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initial begin
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$error("Error: unknown style setting!");
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$finish;
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end
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end
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endgenerate
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endmodule
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