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Enable bitstream compression in example designs

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Alex Forencich 2019-02-06 21:25:30 -08:00
parent 52058cb5de
commit cd6b87e984
4 changed files with 4 additions and 0 deletions
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1
example/NexysVideo/fpga/fpga.xdc
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@ -4,6 +4,7 @@
# General configuration
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
# 100 MHz clock
set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]

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example/VCU108/fpga_10g/fpga.xdc
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@ -4,6 +4,7 @@
# General configuration
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
# System clocks
# 300 MHz

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example/VCU108/fpga_1g/fpga.xdc
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@ -4,6 +4,7 @@
# General configuration
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
# System clocks
# 300 MHz

1
example/VCU118/fpga_1g/fpga.xdc
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@ -4,6 +4,7 @@
# General configuration
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
# System clocks
# 300 MHz