FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Put PHY interface registers into IOBs for timing

Browse Source
This commit is contained in:
Alex Forencich 2015-02-28 18:24:20 -08:00
parent 7532915bb7
commit d57c857d88
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
rtl/gmii_phy_if.v
View File

@ -155,8 +155,11 @@ always @(posedge mac_gmii_rx_clk or posedge rst) begin
end end
// register RX data from PHY to MAC // register RX data from PHY to MAC
(* IOB = "TRUE" *)
reg [7:0] gmii_rxd_reg = 0; reg [7:0] gmii_rxd_reg = 0;
(* IOB = "TRUE" *)
reg gmii_rx_dv_reg = 0; reg gmii_rx_dv_reg = 0;
(* IOB = "TRUE" *)
reg gmii_rx_er_reg = 0; reg gmii_rx_er_reg = 0;
always @(posedge phy_gmii_rx_clk_io) begin always @(posedge phy_gmii_rx_clk_io) begin
@ -170,8 +173,11 @@ assign mac_gmii_rx_dv = gmii_rx_dv_reg;
assign mac_gmii_rx_er = gmii_rx_er_reg; assign mac_gmii_rx_er = gmii_rx_er_reg;
// register TX data from MAC to PHY // register TX data from MAC to PHY
(* IOB = "TRUE" *)
reg [7:0] gmii_txd_reg = 0; reg [7:0] gmii_txd_reg = 0;
(* IOB = "TRUE" *)
reg gmii_tx_en_reg = 0; reg gmii_tx_en_reg = 0;
(* IOB = "TRUE" *)
reg gmii_tx_er_reg = 0; reg gmii_tx_er_reg = 0;
always @(posedge phy_gmii_tx_clk_int) begin always @(posedge phy_gmii_tx_clk_int) begin