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https://github.com/alexforencich/verilog-ethernet.git
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Put PHY interface registers into IOBs for timing
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@ -155,8 +155,11 @@ always @(posedge mac_gmii_rx_clk or posedge rst) begin
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end
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// register RX data from PHY to MAC
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(* IOB = "TRUE" *)
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reg [7:0] gmii_rxd_reg = 0;
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(* IOB = "TRUE" *)
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reg gmii_rx_dv_reg = 0;
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(* IOB = "TRUE" *)
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reg gmii_rx_er_reg = 0;
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always @(posedge phy_gmii_rx_clk_io) begin
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@ -170,8 +173,11 @@ assign mac_gmii_rx_dv = gmii_rx_dv_reg;
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assign mac_gmii_rx_er = gmii_rx_er_reg;
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// register TX data from MAC to PHY
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(* IOB = "TRUE" *)
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reg [7:0] gmii_txd_reg = 0;
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(* IOB = "TRUE" *)
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reg gmii_tx_en_reg = 0;
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(* IOB = "TRUE" *)
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reg gmii_tx_er_reg = 0;
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always @(posedge phy_gmii_tx_clk_int) begin
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