FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Update XDC

Browse Source
This commit is contained in:
Alex Forencich 2020-08-06 22:06:40 -07:00
parent 2e3f2c97b6
commit d97e95b6c7
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
example/ZCU106/fpga/fpga.xdc
View File

@ -46,6 +46,12 @@ set_property -dict {LOC AH17 IOSTANDARD LVCMOS12} [get_ports uart_rxd]
set_property -dict {LOC AM15 IOSTANDARD LVCMOS12} [get_ports uart_rts]
set_property -dict {LOC AP17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_cts]
# I2C interfaces
#set_property -dict {LOC AE19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c0_scl]
#set_property -dict {LOC AH23 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c0_sda]
#set_property -dict {LOC AH19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c1_scl]
#set_property -dict {LOC AL21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c1_sda]
# SFP+ Interface
set_property -dict {LOC AA2 } [get_ports sfp0_rx_p] ;# MGTYRXP2_225 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
#set_property -dict {LOC AA1 } [get_ports sfp0_rx_n] ;# MGTYRXN2_225 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2