FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

merged changes in axis

Browse Source
This commit is contained in:
Alex Forencich 2017-05-18 13:52:23 -07:00
commit db3bbfdf20
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/axis/tb/axis_ep.py
View File

@ -169,6 +169,7 @@ class AXIStreamFrame(object):
def __eq__(self, other):
if type(other) is AXIStreamFrame:
return self.data == other.data
return False
def __repr__(self):
return 'AXIStreamFrame(data=%s, keep=%s, dest=%s, user=%s)' % (repr(self.data), repr(self.keep), repr(self.dest), repr(self.user))