mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
Rename status outputs
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ebe9d17bd5
commit
ded363b471
@ -79,9 +79,9 @@ module axis_fifo #
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/*
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* Status
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*/
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output wire overflow,
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output wire bad_frame,
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output wire good_frame
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output wire status_overflow,
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output wire status_bad_frame,
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output wire status_good_frame
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);
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// check configuration
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@ -168,9 +168,9 @@ assign m_axis_tid = ID_ENABLE ? m_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_
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assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
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assign overflow = overflow_reg;
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assign bad_frame = bad_frame_reg;
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assign good_frame = good_frame_reg;
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assign status_overflow = overflow_reg;
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assign status_bad_frame = bad_frame_reg;
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assign status_good_frame = good_frame_reg;
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// Write logic
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always @* begin
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@ -248,6 +248,7 @@ class AXIStreamFrame(object):
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class AXIStreamSource(object):
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def __init__(self):
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self.active = False
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self.has_logic = False
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self.queue = []
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@ -263,6 +264,13 @@ class AXIStreamSource(object):
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def empty(self):
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return not self.queue
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def idle(self):
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return not self.queue and not self.active
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def wait(self):
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while not self.idle():
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yield self.clk.posedge
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def create_logic(self,
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clk,
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rst,
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@ -289,7 +297,7 @@ class AXIStreamSource(object):
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id = []
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dest = []
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user = []
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valid = False
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self.active = False
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B = 0
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N = len(tdata)
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M = len(tkeep)
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@ -311,7 +319,7 @@ class AXIStreamSource(object):
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id = []
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dest = []
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user = []
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valid = False
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self.active = False
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if B > 0:
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for s in tdata:
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s.next = 0
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@ -324,7 +332,7 @@ class AXIStreamSource(object):
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tvalid.next = False
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tlast.next = False
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else:
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tvalid.next = valid and (tvalid or not pause)
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tvalid.next = self.active and (tvalid or not pause)
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if tready and tvalid:
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if len(data) > 0:
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if B > 0:
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@ -342,8 +350,8 @@ class AXIStreamSource(object):
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else:
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tvalid.next = False
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tlast.next = False
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valid = False
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if not valid and self.queue:
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self.active = False
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if not self.active and self.queue:
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frame = self.queue.pop(0)
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frame.B = B
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frame.N = N
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@ -364,13 +372,14 @@ class AXIStreamSource(object):
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tuser.next = user.pop(0)
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tvalid.next = not pause
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tlast.next = len(data) == 0
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valid = True
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self.active = True
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return instances()
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class AXIStreamSink(object):
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def __init__(self):
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self.active = False
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self.has_logic = False
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self.queue = []
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self.read_queue = []
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@ -396,6 +405,9 @@ class AXIStreamSink(object):
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def empty(self):
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return not self.queue
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def idle(self):
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return not self.active
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def wait(self, timeout=0):
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if self.queue:
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return
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@ -462,6 +474,7 @@ class AXIStreamSink(object):
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dest = []
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user = []
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first = True
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self.active = False
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else:
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tready_int.next = True
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@ -498,6 +511,7 @@ class AXIStreamSink(object):
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dest.append(int(tdest))
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user.append(int(tuser))
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first = False
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self.active = True
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if tlast:
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frame = AXIStreamFrame()
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frame.B = B
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@ -507,6 +521,7 @@ class AXIStreamSink(object):
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frame.parse(data, keep, id, dest, user)
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self.queue.append(frame)
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self.sync.next = not self.sync
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self.active = False
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if name is not None:
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print("[%s] Got frame %s" % (name, repr(frame)))
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data = []
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@ -144,9 +144,9 @@ UUT (
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.m_axis_tdest(m_axis_tdest),
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.m_axis_tuser(m_axis_tuser),
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// Status
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.overflow(),
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.bad_frame(),
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.good_frame()
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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endmodule
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@ -144,9 +144,9 @@ UUT (
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.m_axis_tdest(m_axis_tdest),
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.m_axis_tuser(m_axis_tuser),
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// Status
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.overflow(),
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.bad_frame(),
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.good_frame()
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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endmodule
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@ -83,9 +83,9 @@ def bench():
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m_axis_tid = Signal(intbv(0)[ID_WIDTH:])
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m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
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m_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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overflow = Signal(bool(0))
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bad_frame = Signal(bool(0))
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good_frame = Signal(bool(0))
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status_overflow = Signal(bool(0))
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status_bad_frame = Signal(bool(0))
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status_good_frame = Signal(bool(0))
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# sources and sinks
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source_pause = Signal(bool(0))
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@ -153,27 +153,27 @@ def bench():
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m_axis_tdest=m_axis_tdest,
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m_axis_tuser=m_axis_tuser,
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overflow=overflow,
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bad_frame=bad_frame,
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good_frame=good_frame
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status_overflow=status_overflow,
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status_bad_frame=status_bad_frame,
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status_good_frame=status_good_frame
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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overflow_asserted = Signal(bool(0))
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bad_frame_asserted = Signal(bool(0))
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good_frame_asserted = Signal(bool(0))
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status_overflow_asserted = Signal(bool(0))
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status_bad_frame_asserted = Signal(bool(0))
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status_good_frame_asserted = Signal(bool(0))
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@always(clk.posedge)
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def monitor():
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if (overflow):
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overflow_asserted.next = 1
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if (bad_frame):
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bad_frame_asserted.next = 1
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if (good_frame):
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good_frame_asserted.next = 1
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if (status_overflow):
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status_overflow_asserted.next = 1
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if (status_bad_frame):
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status_bad_frame_asserted.next = 1
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if (status_good_frame):
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status_good_frame_asserted.next = 1
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@instance
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def check():
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@ -201,9 +201,9 @@ def bench():
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dest=1
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame)
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@ -212,9 +212,9 @@ def bench():
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assert rx_frame == test_frame
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assert not overflow_asserted
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assert not bad_frame_asserted
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assert good_frame_asserted
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assert not status_overflow_asserted
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assert not status_bad_frame_asserted
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assert status_good_frame_asserted
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yield delay(100)
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@ -231,9 +231,9 @@ def bench():
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dest=1
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame)
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@ -242,9 +242,9 @@ def bench():
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assert rx_frame == test_frame
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assert not overflow_asserted
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assert not bad_frame_asserted
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assert good_frame_asserted
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assert not status_overflow_asserted
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assert not status_bad_frame_asserted
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assert status_good_frame_asserted
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yield clk.posedge
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print("test 3: test packet with pauses")
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@ -259,9 +259,9 @@ def bench():
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dest=1
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield clk.posedge
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@ -285,9 +285,9 @@ def bench():
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assert rx_frame == test_frame
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assert not overflow_asserted
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assert not bad_frame_asserted
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assert good_frame_asserted
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assert not status_overflow_asserted
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assert not status_bad_frame_asserted
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assert status_good_frame_asserted
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yield delay(100)
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@ -312,9 +312,9 @@ def bench():
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dest=2
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame1)
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source.send(test_frame2)
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@ -329,9 +329,9 @@ def bench():
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assert rx_frame == test_frame2
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assert not overflow_asserted
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assert not bad_frame_asserted
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assert good_frame_asserted
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assert not status_overflow_asserted
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assert not status_bad_frame_asserted
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assert status_good_frame_asserted
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yield delay(100)
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@ -356,9 +356,9 @@ def bench():
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dest=2
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame1)
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source.send(test_frame2)
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@ -382,9 +382,9 @@ def bench():
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assert rx_frame == test_frame2
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assert not overflow_asserted
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assert not bad_frame_asserted
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assert good_frame_asserted
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assert not status_overflow_asserted
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assert not status_bad_frame_asserted
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assert status_good_frame_asserted
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yield delay(100)
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@ -409,9 +409,9 @@ def bench():
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dest=2
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame1)
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source.send(test_frame2)
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@ -435,9 +435,9 @@ def bench():
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assert rx_frame == test_frame2
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assert not overflow_asserted
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assert not bad_frame_asserted
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assert good_frame_asserted
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assert not status_overflow_asserted
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assert not status_bad_frame_asserted
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assert status_good_frame_asserted
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yield delay(100)
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@ -455,9 +455,9 @@ def bench():
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last_cycle_user=1
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield clk.posedge
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@ -466,9 +466,9 @@ def bench():
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assert sink.empty()
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assert not overflow_asserted
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assert bad_frame_asserted
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assert not good_frame_asserted
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assert not status_overflow_asserted
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assert status_bad_frame_asserted
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assert not status_good_frame_asserted
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yield delay(100)
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@ -485,9 +485,9 @@ def bench():
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dest=1
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)
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overflow_asserted.next = 0
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bad_frame_asserted.next = 0
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good_frame_asserted.next = 0
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status_overflow_asserted.next = 0
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status_bad_frame_asserted.next = 0
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status_good_frame_asserted.next = 0
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source.send(test_frame)
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yield clk.posedge
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@ -496,9 +496,9 @@ def bench():
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assert sink.empty()
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assert overflow_asserted
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assert not bad_frame_asserted
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assert not good_frame_asserted
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assert status_overflow_asserted
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assert not status_bad_frame_asserted
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assert not status_good_frame_asserted
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yield delay(100)
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@ -72,9 +72,9 @@ wire m_axis_tlast;
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wire [ID_WIDTH-1:0] m_axis_tid;
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wire [DEST_WIDTH-1:0] m_axis_tdest;
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wire [USER_WIDTH-1:0] m_axis_tuser;
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wire overflow;
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wire bad_frame;
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wire good_frame;
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wire status_overflow;
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wire status_bad_frame;
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wire status_good_frame;
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initial begin
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// myhdl integration
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@ -100,9 +100,9 @@ initial begin
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m_axis_tid,
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m_axis_tdest,
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m_axis_tuser,
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overflow,
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bad_frame,
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good_frame
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status_overflow,
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status_bad_frame,
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status_good_frame
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);
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// dump file
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@ -150,9 +150,9 @@ UUT (
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.m_axis_tdest(m_axis_tdest),
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.m_axis_tuser(m_axis_tuser),
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// Status
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.overflow(overflow),
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.bad_frame(bad_frame),
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.good_frame(good_frame)
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.status_overflow(status_overflow),
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.status_bad_frame(status_bad_frame),
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.status_good_frame(status_good_frame)
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);
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endmodule
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@ -83,9 +83,9 @@ def bench():
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m_axis_tid = Signal(intbv(0)[ID_WIDTH:])
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m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
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m_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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overflow = Signal(bool(0))
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bad_frame = Signal(bool(0))
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good_frame = Signal(bool(0))
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status_overflow = Signal(bool(0))
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status_bad_frame = Signal(bool(0))
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status_good_frame = Signal(bool(0))
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# sources and sinks
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source_pause = Signal(bool(0))
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@ -153,27 +153,27 @@ def bench():
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m_axis_tdest=m_axis_tdest,
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m_axis_tuser=m_axis_tuser,
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overflow=overflow,
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bad_frame=bad_frame,
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good_frame=good_frame
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status_overflow=status_overflow,
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status_bad_frame=status_bad_frame,
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status_good_frame=status_good_frame
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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overflow_asserted = Signal(bool(0))
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bad_frame_asserted = Signal(bool(0))
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good_frame_asserted = Signal(bool(0))
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status_overflow_asserted = Signal(bool(0))
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status_bad_frame_asserted = Signal(bool(0))
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status_good_frame_asserted = Signal(bool(0))
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@always(clk.posedge)
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def monitor():
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if (overflow):
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overflow_asserted.next = 1
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if (bad_frame):
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bad_frame_asserted.next = 1
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if (good_frame):
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good_frame_asserted.next = 1
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if (status_overflow):
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status_overflow_asserted.next = 1
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if (status_bad_frame):
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status_bad_frame_asserted.next = 1
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if (status_good_frame):
|
||||
status_good_frame_asserted.next = 1
|
||||
|
||||
@instance
|
||||
def check():
|
||||
@ -201,9 +201,9 @@ def bench():
|
||||
dest=1
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame)
|
||||
|
||||
@ -212,9 +212,9 @@ def bench():
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
assert not overflow_asserted
|
||||
assert not bad_frame_asserted
|
||||
assert good_frame_asserted
|
||||
assert not status_overflow_asserted
|
||||
assert not status_bad_frame_asserted
|
||||
assert status_good_frame_asserted
|
||||
|
||||
yield delay(100)
|
||||
|
||||
@ -231,9 +231,9 @@ def bench():
|
||||
dest=1
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame)
|
||||
|
||||
@ -242,9 +242,9 @@ def bench():
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
assert not overflow_asserted
|
||||
assert not bad_frame_asserted
|
||||
assert good_frame_asserted
|
||||
assert not status_overflow_asserted
|
||||
assert not status_bad_frame_asserted
|
||||
assert status_good_frame_asserted
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: test packet with pauses")
|
||||
@ -259,9 +259,9 @@ def bench():
|
||||
dest=1
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
@ -285,9 +285,9 @@ def bench():
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
assert not overflow_asserted
|
||||
assert not bad_frame_asserted
|
||||
assert good_frame_asserted
|
||||
assert not status_overflow_asserted
|
||||
assert not status_bad_frame_asserted
|
||||
assert status_good_frame_asserted
|
||||
|
||||
yield delay(100)
|
||||
|
||||
@ -312,9 +312,9 @@ def bench():
|
||||
dest=2
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
@ -329,9 +329,9 @@ def bench():
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
assert not overflow_asserted
|
||||
assert not bad_frame_asserted
|
||||
assert good_frame_asserted
|
||||
assert not status_overflow_asserted
|
||||
assert not status_bad_frame_asserted
|
||||
assert status_good_frame_asserted
|
||||
|
||||
yield delay(100)
|
||||
|
||||
@ -356,9 +356,9 @@ def bench():
|
||||
dest=2
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
@ -382,9 +382,9 @@ def bench():
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
assert not overflow_asserted
|
||||
assert not bad_frame_asserted
|
||||
assert good_frame_asserted
|
||||
assert not status_overflow_asserted
|
||||
assert not status_bad_frame_asserted
|
||||
assert status_good_frame_asserted
|
||||
|
||||
yield delay(100)
|
||||
|
||||
@ -409,9 +409,9 @@ def bench():
|
||||
dest=2
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame1)
|
||||
source.send(test_frame2)
|
||||
@ -435,9 +435,9 @@ def bench():
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
assert not overflow_asserted
|
||||
assert not bad_frame_asserted
|
||||
assert good_frame_asserted
|
||||
assert not status_overflow_asserted
|
||||
assert not status_bad_frame_asserted
|
||||
assert status_good_frame_asserted
|
||||
|
||||
yield delay(100)
|
||||
|
||||
@ -455,9 +455,9 @@ def bench():
|
||||
last_cycle_user=1
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
@ -466,9 +466,9 @@ def bench():
|
||||
|
||||
assert sink.empty()
|
||||
|
||||
assert not overflow_asserted
|
||||
assert bad_frame_asserted
|
||||
assert not good_frame_asserted
|
||||
assert not status_overflow_asserted
|
||||
assert status_bad_frame_asserted
|
||||
assert not status_good_frame_asserted
|
||||
|
||||
yield delay(100)
|
||||
|
||||
@ -485,9 +485,9 @@ def bench():
|
||||
dest=1
|
||||
)
|
||||
|
||||
overflow_asserted.next = 0
|
||||
bad_frame_asserted.next = 0
|
||||
good_frame_asserted.next = 0
|
||||
status_overflow_asserted.next = 0
|
||||
status_bad_frame_asserted.next = 0
|
||||
status_good_frame_asserted.next = 0
|
||||
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
@ -496,9 +496,9 @@ def bench():
|
||||
|
||||
assert sink.empty()
|
||||
|
||||
assert overflow_asserted
|
||||
assert not bad_frame_asserted
|
||||
assert not good_frame_asserted
|
||||
assert status_overflow_asserted
|
||||
assert not status_bad_frame_asserted
|
||||
assert not status_good_frame_asserted
|
||||
|
||||
yield delay(100)
|
||||
|
||||
|
@ -72,9 +72,9 @@ wire m_axis_tlast;
|
||||
wire [ID_WIDTH-1:0] m_axis_tid;
|
||||
wire [DEST_WIDTH-1:0] m_axis_tdest;
|
||||
wire [USER_WIDTH-1:0] m_axis_tuser;
|
||||
wire overflow;
|
||||
wire bad_frame;
|
||||
wire good_frame;
|
||||
wire status_overflow;
|
||||
wire status_bad_frame;
|
||||
wire status_good_frame;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
@ -100,9 +100,9 @@ initial begin
|
||||
m_axis_tid,
|
||||
m_axis_tdest,
|
||||
m_axis_tuser,
|
||||
overflow,
|
||||
bad_frame,
|
||||
good_frame
|
||||
status_overflow,
|
||||
status_bad_frame,
|
||||
status_good_frame
|
||||
);
|
||||
|
||||
// dump file
|
||||
@ -150,9 +150,9 @@ UUT (
|
||||
.m_axis_tdest(m_axis_tdest),
|
||||
.m_axis_tuser(m_axis_tuser),
|
||||
// Status
|
||||
.overflow(overflow),
|
||||
.bad_frame(bad_frame),
|
||||
.good_frame(good_frame)
|
||||
.status_overflow(status_overflow),
|
||||
.status_bad_frame(status_bad_frame),
|
||||
.status_good_frame(status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
Loading…
x
Reference in New Issue
Block a user