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Rename status outputs

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This commit is contained in:
Alex Forencich 2018-10-25 15:36:34 -07:00
parent ebe9d17bd5
commit ded363b471
8 changed files with 177 additions and 162 deletions
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12
rtl/axis_fifo.v
View File

@ -79,9 +79,9 @@ module axis_fifo #
/* /*
* Status * Status
*/ */
output wire overflow, output wire status_overflow,
output wire bad_frame, output wire status_bad_frame,
output wire good_frame output wire status_good_frame
); );
// check configuration // check configuration
@ -168,9 +168,9 @@ assign m_axis_tid = ID_ENABLE ? m_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_
assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
assign overflow = overflow_reg; assign status_overflow = overflow_reg;
assign bad_frame = bad_frame_reg; assign status_bad_frame = bad_frame_reg;
assign good_frame = good_frame_reg; assign status_good_frame = good_frame_reg;
// Write logic // Write logic
always @* begin always @* begin

27
tb/axis_ep.py
View File

@ -248,6 +248,7 @@ class AXIStreamFrame(object):
class AXIStreamSource(object): class AXIStreamSource(object):
def __init__(self): def __init__(self):
self.active = False
self.has_logic = False self.has_logic = False
self.queue = [] self.queue = []
@ -263,6 +264,13 @@ class AXIStreamSource(object):
def empty(self): def empty(self):
return not self.queue return not self.queue
def idle(self):
return not self.queue and not self.active
def wait(self):
while not self.idle():
yield self.clk.posedge
def create_logic(self, def create_logic(self,
clk, clk,
rst, rst,
@ -289,7 +297,7 @@ class AXIStreamSource(object):
id = [] id = []
dest = [] dest = []
user = [] user = []
valid = False self.active = False
B = 0 B = 0
N = len(tdata) N = len(tdata)
M = len(tkeep) M = len(tkeep)
@ -311,7 +319,7 @@ class AXIStreamSource(object):
id = [] id = []
dest = [] dest = []
user = [] user = []
valid = False self.active = False
if B > 0: if B > 0:
for s in tdata: for s in tdata:
s.next = 0 s.next = 0
@ -324,7 +332,7 @@ class AXIStreamSource(object):
tvalid.next = False tvalid.next = False
tlast.next = False tlast.next = False
else: else:
tvalid.next = valid and (tvalid or not pause) tvalid.next = self.active and (tvalid or not pause)
if tready and tvalid: if tready and tvalid:
if len(data) > 0: if len(data) > 0:
if B > 0: if B > 0:
@ -342,8 +350,8 @@ class AXIStreamSource(object):
else: else:
tvalid.next = False tvalid.next = False
tlast.next = False tlast.next = False
valid = False self.active = False
if not valid and self.queue: if not self.active and self.queue:
frame = self.queue.pop(0) frame = self.queue.pop(0)
frame.B = B frame.B = B
frame.N = N frame.N = N
@ -364,13 +372,14 @@ class AXIStreamSource(object):
tuser.next = user.pop(0) tuser.next = user.pop(0)
tvalid.next = not pause tvalid.next = not pause
tlast.next = len(data) == 0 tlast.next = len(data) == 0
valid = True self.active = True
return instances() return instances()
class AXIStreamSink(object): class AXIStreamSink(object):
def __init__(self): def __init__(self):
self.active = False
self.has_logic = False self.has_logic = False
self.queue = [] self.queue = []
self.read_queue = [] self.read_queue = []
@ -396,6 +405,9 @@ class AXIStreamSink(object):
def empty(self): def empty(self):
return not self.queue return not self.queue
def idle(self):
return not self.active
def wait(self, timeout=0): def wait(self, timeout=0):
if self.queue: if self.queue:
return return
@ -462,6 +474,7 @@ class AXIStreamSink(object):
dest = [] dest = []
user = [] user = []
first = True first = True
self.active = False
else: else:
tready_int.next = True tready_int.next = True
@ -498,6 +511,7 @@ class AXIStreamSink(object):
dest.append(int(tdest)) dest.append(int(tdest))
user.append(int(tuser)) user.append(int(tuser))
first = False first = False
self.active = True
if tlast: if tlast:
frame = AXIStreamFrame() frame = AXIStreamFrame()
frame.B = B frame.B = B
@ -507,6 +521,7 @@ class AXIStreamSink(object):
frame.parse(data, keep, id, dest, user) frame.parse(data, keep, id, dest, user)
self.queue.append(frame) self.queue.append(frame)
self.sync.next = not self.sync self.sync.next = not self.sync
self.active = False
if name is not None: if name is not None:
print("[%s] Got frame %s" % (name, repr(frame))) print("[%s] Got frame %s" % (name, repr(frame)))
data = [] data = []

6
tb/test_axis_fifo.v
View File

@ -144,9 +144,9 @@ UUT (
.m_axis_tdest(m_axis_tdest), .m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser), .m_axis_tuser(m_axis_tuser),
// Status // Status
.overflow(), .status_overflow(),
.bad_frame(), .status_bad_frame(),
.good_frame() .status_good_frame()
); );
endmodule endmodule

6
tb/test_axis_fifo_64.v
View File

@ -144,9 +144,9 @@ UUT (
.m_axis_tdest(m_axis_tdest), .m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser), .m_axis_tuser(m_axis_tuser),
// Status // Status
.overflow(), .status_overflow(),
.bad_frame(), .status_bad_frame(),
.good_frame() .status_good_frame()
); );
endmodule endmodule

126
tb/test_axis_frame_fifo.py
View File

@ -83,9 +83,9 @@ def bench():
m_axis_tid = Signal(intbv(0)[ID_WIDTH:]) m_axis_tid = Signal(intbv(0)[ID_WIDTH:])
m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:]) m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
m_axis_tuser = Signal(intbv(0)[USER_WIDTH:]) m_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
overflow = Signal(bool(0)) status_overflow = Signal(bool(0))
bad_frame = Signal(bool(0)) status_bad_frame = Signal(bool(0))
good_frame = Signal(bool(0)) status_good_frame = Signal(bool(0))
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -153,27 +153,27 @@ def bench():
m_axis_tdest=m_axis_tdest, m_axis_tdest=m_axis_tdest,
m_axis_tuser=m_axis_tuser, m_axis_tuser=m_axis_tuser,
overflow=overflow, status_overflow=status_overflow,
bad_frame=bad_frame, status_bad_frame=status_bad_frame,
good_frame=good_frame status_good_frame=status_good_frame
) )
@always(delay(4)) @always(delay(4))
def clkgen(): def clkgen():
clk.next = not clk clk.next = not clk
overflow_asserted = Signal(bool(0)) status_overflow_asserted = Signal(bool(0))
bad_frame_asserted = Signal(bool(0)) status_bad_frame_asserted = Signal(bool(0))
good_frame_asserted = Signal(bool(0)) status_good_frame_asserted = Signal(bool(0))
@always(clk.posedge) @always(clk.posedge)
def monitor(): def monitor():
if (overflow): if (status_overflow):
overflow_asserted.next = 1 status_overflow_asserted.next = 1
if (bad_frame): if (status_bad_frame):
bad_frame_asserted.next = 1 status_bad_frame_asserted.next = 1
if (good_frame): if (status_good_frame):
good_frame_asserted.next = 1 status_good_frame_asserted.next = 1
@instance @instance
def check(): def check():
@ -201,9 +201,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
@ -212,9 +212,9 @@ def bench():
assert rx_frame == test_frame assert rx_frame == test_frame
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -231,9 +231,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
@ -242,9 +242,9 @@ def bench():
assert rx_frame == test_frame assert rx_frame == test_frame
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield clk.posedge yield clk.posedge
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
@ -259,9 +259,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -285,9 +285,9 @@ def bench():
assert rx_frame == test_frame assert rx_frame == test_frame
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -312,9 +312,9 @@ def bench():
dest=2 dest=2
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
@ -329,9 +329,9 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -356,9 +356,9 @@ def bench():
dest=2 dest=2
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
@ -382,9 +382,9 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -409,9 +409,9 @@ def bench():
dest=2 dest=2
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
@ -435,9 +435,9 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -455,9 +455,9 @@ def bench():
last_cycle_user=1 last_cycle_user=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -466,9 +466,9 @@ def bench():
assert sink.empty() assert sink.empty()
assert not overflow_asserted assert not status_overflow_asserted
assert bad_frame_asserted assert status_bad_frame_asserted
assert not good_frame_asserted assert not status_good_frame_asserted
yield delay(100) yield delay(100)
@ -485,9 +485,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -496,9 +496,9 @@ def bench():
assert sink.empty() assert sink.empty()
assert overflow_asserted assert status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert not good_frame_asserted assert not status_good_frame_asserted
yield delay(100) yield delay(100)

18
tb/test_axis_frame_fifo.v
View File

@ -72,9 +72,9 @@ wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid; wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest; wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser; wire [USER_WIDTH-1:0] m_axis_tuser;
wire overflow; wire status_overflow;
wire bad_frame; wire status_bad_frame;
wire good_frame; wire status_good_frame;
initial begin initial begin
// myhdl integration // myhdl integration
@ -100,9 +100,9 @@ initial begin
m_axis_tid, m_axis_tid,
m_axis_tdest, m_axis_tdest,
m_axis_tuser, m_axis_tuser,
overflow, status_overflow,
bad_frame, status_bad_frame,
good_frame status_good_frame
); );
// dump file // dump file
@ -150,9 +150,9 @@ UUT (
.m_axis_tdest(m_axis_tdest), .m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser), .m_axis_tuser(m_axis_tuser),
// Status // Status
.overflow(overflow), .status_overflow(status_overflow),
.bad_frame(bad_frame), .status_bad_frame(status_bad_frame),
.good_frame(good_frame) .status_good_frame(status_good_frame)
); );
endmodule endmodule

126
tb/test_axis_frame_fifo_64.py
View File

@ -83,9 +83,9 @@ def bench():
m_axis_tid = Signal(intbv(0)[ID_WIDTH:]) m_axis_tid = Signal(intbv(0)[ID_WIDTH:])
m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:]) m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
m_axis_tuser = Signal(intbv(0)[USER_WIDTH:]) m_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
overflow = Signal(bool(0)) status_overflow = Signal(bool(0))
bad_frame = Signal(bool(0)) status_bad_frame = Signal(bool(0))
good_frame = Signal(bool(0)) status_good_frame = Signal(bool(0))
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -153,27 +153,27 @@ def bench():
m_axis_tdest=m_axis_tdest, m_axis_tdest=m_axis_tdest,
m_axis_tuser=m_axis_tuser, m_axis_tuser=m_axis_tuser,
overflow=overflow, status_overflow=status_overflow,
bad_frame=bad_frame, status_bad_frame=status_bad_frame,
good_frame=good_frame status_good_frame=status_good_frame
) )
@always(delay(4)) @always(delay(4))
def clkgen(): def clkgen():
clk.next = not clk clk.next = not clk
overflow_asserted = Signal(bool(0)) status_overflow_asserted = Signal(bool(0))
bad_frame_asserted = Signal(bool(0)) status_bad_frame_asserted = Signal(bool(0))
good_frame_asserted = Signal(bool(0)) status_good_frame_asserted = Signal(bool(0))
@always(clk.posedge) @always(clk.posedge)
def monitor(): def monitor():
if (overflow): if (status_overflow):
overflow_asserted.next = 1 status_overflow_asserted.next = 1
if (bad_frame): if (status_bad_frame):
bad_frame_asserted.next = 1 status_bad_frame_asserted.next = 1
if (good_frame): if (status_good_frame):
good_frame_asserted.next = 1 status_good_frame_asserted.next = 1
@instance @instance
def check(): def check():
@ -201,9 +201,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
@ -212,9 +212,9 @@ def bench():
assert rx_frame == test_frame assert rx_frame == test_frame
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -231,9 +231,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
@ -242,9 +242,9 @@ def bench():
assert rx_frame == test_frame assert rx_frame == test_frame
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield clk.posedge yield clk.posedge
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
@ -259,9 +259,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -285,9 +285,9 @@ def bench():
assert rx_frame == test_frame assert rx_frame == test_frame
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -312,9 +312,9 @@ def bench():
dest=2 dest=2
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
@ -329,9 +329,9 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -356,9 +356,9 @@ def bench():
dest=2 dest=2
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
@ -382,9 +382,9 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -409,9 +409,9 @@ def bench():
dest=2 dest=2
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
@ -435,9 +435,9 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
assert not overflow_asserted assert not status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert good_frame_asserted assert status_good_frame_asserted
yield delay(100) yield delay(100)
@ -455,9 +455,9 @@ def bench():
last_cycle_user=1 last_cycle_user=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -466,9 +466,9 @@ def bench():
assert sink.empty() assert sink.empty()
assert not overflow_asserted assert not status_overflow_asserted
assert bad_frame_asserted assert status_bad_frame_asserted
assert not good_frame_asserted assert not status_good_frame_asserted
yield delay(100) yield delay(100)
@ -485,9 +485,9 @@ def bench():
dest=1 dest=1
) )
overflow_asserted.next = 0 status_overflow_asserted.next = 0
bad_frame_asserted.next = 0 status_bad_frame_asserted.next = 0
good_frame_asserted.next = 0 status_good_frame_asserted.next = 0
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -496,9 +496,9 @@ def bench():
assert sink.empty() assert sink.empty()
assert overflow_asserted assert status_overflow_asserted
assert not bad_frame_asserted assert not status_bad_frame_asserted
assert not good_frame_asserted assert not status_good_frame_asserted
yield delay(100) yield delay(100)

18
tb/test_axis_frame_fifo_64.v
View File

@ -72,9 +72,9 @@ wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid; wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest; wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser; wire [USER_WIDTH-1:0] m_axis_tuser;
wire overflow; wire status_overflow;
wire bad_frame; wire status_bad_frame;
wire good_frame; wire status_good_frame;
initial begin initial begin
// myhdl integration // myhdl integration
@ -100,9 +100,9 @@ initial begin
m_axis_tid, m_axis_tid,
m_axis_tdest, m_axis_tdest,
m_axis_tuser, m_axis_tuser,
overflow, status_overflow,
bad_frame, status_bad_frame,
good_frame status_good_frame
); );
// dump file // dump file
@ -150,9 +150,9 @@ UUT (
.m_axis_tdest(m_axis_tdest), .m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser), .m_axis_tuser(m_axis_tuser),
// Status // Status
.overflow(overflow), .status_overflow(status_overflow),
.bad_frame(bad_frame), .status_bad_frame(status_bad_frame),
.good_frame(good_frame) .status_good_frame(status_good_frame)
); );
endmodule endmodule