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Use correct clock

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This commit is contained in:
Alex Forencich 2019-03-28 17:56:55 -07:00
parent 58201866f3
commit e120a85607
2 changed files with 8 additions and 8 deletions
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8
example/VCU108/fpga_10g/rtl/fpga.v
View File

@ -218,11 +218,11 @@ wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
@ -245,7 +245,7 @@ sync_signal #(
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.clk(clk_156mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);

8
example/VCU118/fpga_10g/rtl/fpga.v
View File

@ -248,11 +248,11 @@ wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
@ -275,7 +275,7 @@ sync_signal #(
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.clk(clk_156mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);