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Update ML605 reference design

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This commit is contained in:
Alex Forencich 2017-05-31 19:52:43 -07:00
parent 9fdc36450a
commit e376c805d2
7 changed files with 54 additions and 63 deletions
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2
example/ML605/fpga/clock.ucf
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@ -1,6 +1,6 @@
# UCF file for clock module domain crossing constraints
NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int";
NET "core_inst/gmii_rx_clk" TNM = "ffs_gmii_rx_clk";
NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk";
TIMESPEC "TS_clk_125mhz_int_to_gmii_rx_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_gmii_rx_clk" 10 ns;
TIMESPEC "TS_gmii_rx_clk_to_clk_125mhz_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_125mhz_int" 10 ns;

3
example/ML605/fpga/fpga.ucf
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@ -52,6 +52,7 @@ NET "phy_reset_n" LOC = "AH13" | IOSTANDARD=LVCMOS25; # Bank = 33, IO_L18P_33 (E
#NET "phy_mdio" LOC = "AN14" | IOSTANDARD=LVCMOS25; # (E-MDIO)
# GMII Transmit
NET "phy_gtx_clk" LOC = "AH12" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # Bank = 33, IO_L16N_33 (E-GTXCLK)
NET "phy_tx_clk" LOC = "AD12" | IOSTANDARD=LVCMOS25; # Bank = 33, IO_L10P_MRCC_33 (E-TXCLK)
NET "phy_txd<0>" LOC = "AM11" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # Bank = 33, IO_L7N_33 (E-TXD0)
NET "phy_txd<1>" LOC = "AL11" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # Bank = 33, IO_L7P_33 (E-TXD1)
NET "phy_txd<2>" LOC = "AG10" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # Bank = 33, IO_L6N_33 (E-TXD2)
@ -63,7 +64,7 @@ NET "phy_txd<7>" LOC = "AF11" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # Bank = 33,
NET "phy_tx_en" LOC = "AJ10" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # Bank = 33, IO_L8P_SRCC_33 (E-TXEN)
NET "phy_tx_er" LOC = "AH10" | IOSTANDARD=LVCMOS25 | SLEW = FAST; # Bank = 33, IO_L8N_SRCC_33 (E-TXER)
# GMII Receive
NET "phy_rx_clk" LOC = "AP11" | IOSTANDARD=LVCMOS25 | TNM_NET = "clk_rx_local"; # (E-RXCLK)
NET "phy_rx_clk" LOC = "AP11" | IOSTANDARD=LVCMOS25 | TNM_NET = "clk_rx_local"; # (E-RXCLK)
NET "phy_rxd<0>" LOC = "AN13" | IOSTANDARD=LVCMOS25; # Bank = 33, IO_L15P_33 (E-RXD0)
NET "phy_rxd<1>" LOC = "AF14" | IOSTANDARD=LVCMOS25; # Bank = 33, IO_L14N_VREF_33 (E-RXD1)
NET "phy_rxd<2>" LOC = "AE14" | IOSTANDARD=LVCMOS25; # Bank = 33, IO_L14P_33 (E-RXD2)

7
example/ML605/fpga/fpga/Makefile
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@ -19,10 +19,11 @@ SYN_FILES += lib/eth/rtl/oddr.v
SYN_FILES += lib/eth/rtl/ssio_sdr_in.v
SYN_FILES += lib/eth/rtl/ssio_sdr_out.v
SYN_FILES += lib/eth/rtl/gmii_phy_if.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii.v
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_rx.v
SYN_FILES += lib/eth/rtl/eth_mac_1g_tx.v
SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
SYN_FILES += lib/eth/rtl/eth_axis_tx.v

2
example/ML605/fpga/rtl/fpga.v
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@ -60,6 +60,7 @@ module fpga (
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
@ -262,6 +263,7 @@ core_inst (
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),

75
example/ML605/fpga/rtl/fpga_core.v
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@ -65,6 +65,7 @@ module fpga_core #
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
@ -79,19 +80,6 @@ module fpga_core #
output wire uart_cts
);
// GMII between MAC and PHY IF
wire gmii_rx_clk;
wire gmii_rx_rst;
wire [7:0] gmii_rxd;
wire gmii_rx_dv;
wire gmii_rx_er;
wire gmii_tx_clk;
wire gmii_tx_rst;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
@ -335,47 +323,18 @@ assign phy_reset_n = ~rst_125mhz;
assign uart_rxd = 0;
assign uart_cts = 0;
gmii_phy_if #(
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR")
)
gmii_phy_if_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
.mac_gmii_rx_clk(gmii_rx_clk),
.mac_gmii_rx_rst(gmii_rx_rst),
.mac_gmii_rxd(gmii_rxd),
.mac_gmii_rx_dv(gmii_rx_dv),
.mac_gmii_rx_er(gmii_rx_er),
.mac_gmii_tx_clk(gmii_tx_clk),
.mac_gmii_tx_rst(gmii_tx_rst),
.mac_gmii_txd(gmii_txd),
.mac_gmii_tx_en(gmii_tx_en),
.mac_gmii_tx_er(gmii_tx_er),
.phy_gmii_rx_clk(phy_rx_clk),
.phy_gmii_rxd(phy_rxd),
.phy_gmii_rx_dv(phy_rx_dv),
.phy_gmii_rx_er(phy_rx_er),
.phy_gmii_tx_clk(phy_gtx_clk),
.phy_gmii_txd(phy_txd),
.phy_gmii_tx_en(phy_tx_en),
.phy_gmii_tx_er(phy_tx_er)
);
eth_mac_1g_fifo #(
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
)
eth_mac_1g_fifo_inst (
.rx_clk(gmii_rx_clk),
.rx_rst(gmii_rx_rst),
.tx_clk(gmii_tx_clk),
.tx_rst(gmii_tx_rst),
eth_mac_inst (
.gtx_clk(clk_125mhz),
.gtx_rst(rst_125mhz),
.logic_clk(clk_125mhz),
.logic_rst(rst_125mhz),
@ -391,15 +350,25 @@ eth_mac_1g_fifo_inst (
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.gmii_rx_clk(phy_rx_clk),
.gmii_rxd(phy_rxd),
.gmii_rx_dv(phy_rx_dv),
.gmii_rx_er(phy_rx_er),
.gmii_tx_clk(phy_gtx_clk),
.mii_tx_clk(phy_tx_clk),
.gmii_txd(phy_txd),
.gmii_tx_en(phy_tx_en),
.gmii_tx_er(phy_tx_er),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);

25
example/ML605/fpga/tb/test_fpga_core.py
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@ -42,10 +42,11 @@ srcs.append("../lib/eth/rtl/oddr.v")
srcs.append("../lib/eth/rtl/ssio_sdr_in.v")
srcs.append("../lib/eth/rtl/ssio_sdr_out.v")
srcs.append("../lib/eth/rtl/gmii_phy_if.v")
srcs.append("../lib/eth/rtl/eth_mac_1g_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_1g_gmii_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_1g_gmii.v")
srcs.append("../lib/eth/rtl/eth_mac_1g.v")
srcs.append("../lib/eth/rtl/eth_mac_1g_rx.v")
srcs.append("../lib/eth/rtl/eth_mac_1g_tx.v")
srcs.append("../lib/eth/rtl/axis_gmii_rx.v")
srcs.append("../lib/eth/rtl/axis_gmii_tx.v")
srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx.v")
srcs.append("../lib/eth/rtl/eth_axis_tx.v")
@ -98,6 +99,7 @@ def bench():
phy_rxd = Signal(intbv(0)[8:])
phy_rx_dv = Signal(bool(0))
phy_rx_er = Signal(bool(0))
phy_tx_clk = Signal(bool(0))
uart_txd = Signal(bool(0))
uart_rts = Signal(bool(0))
@ -117,6 +119,8 @@ def bench():
uart_cts = Signal(bool(0))
# sources and sinks
mii_select = Signal(bool(0))
gmii_source = gmii_ep.GMIISource()
gmii_source_logic = gmii_source.create_logic(
@ -125,6 +129,7 @@ def bench():
txd=phy_rxd,
tx_en=phy_rx_dv,
tx_er=phy_rx_er,
mii_select=mii_select,
name='gmii_source'
)
@ -136,6 +141,7 @@ def bench():
rxd=phy_txd,
rx_dv=phy_tx_en,
rx_er=phy_tx_er,
mii_select=mii_select,
name='gmii_sink'
)
@ -167,6 +173,7 @@ def bench():
phy_rx_dv=phy_rx_dv,
phy_rx_er=phy_rx_er,
phy_gtx_clk=phy_gtx_clk,
phy_tx_clk=phy_tx_clk,
phy_txd=phy_txd,
phy_tx_en=phy_tx_en,
phy_tx_er=phy_tx_er,
@ -182,7 +189,15 @@ def bench():
def clkgen():
clk.next = not clk
clk_125mhz.next = not clk_125mhz
phy_rx_clk.next = not phy_rx_clk
rx_clk_hp = Signal(int(4))
@instance
def rx_clk_gen():
while True:
yield delay(int(rx_clk_hp))
phy_rx_clk.next = not phy_rx_clk
phy_tx_clk.next = not phy_tx_clk
@instance
def check():
@ -305,7 +320,7 @@ def bench():
raise StopSimulation
return dut, gmii_source_logic, gmii_sink_logic, clkgen, check
return dut, gmii_source_logic, gmii_sink_logic, clkgen, rx_clk_gen, check
def test_bench():
sim = Simulation(bench())

3
example/ML605/fpga/tb/test_fpga_core.v
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@ -49,6 +49,7 @@ reg phy_rx_clk = 0;
reg [7:0] phy_rxd = 0;
reg phy_rx_dv = 0;
reg phy_rx_er = 0;
reg phy_tx_clk = 0;
reg uart_txd = 0;
reg uart_rts = 0;
@ -83,6 +84,7 @@ initial begin
phy_rxd,
phy_rx_dv,
phy_rx_er,
phy_tx_clk,
uart_txd,
uart_rts
);
@ -130,6 +132,7 @@ UUT (
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),