From e4672915e6214fefb3394951d8e88e185c4b5d8d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 13 Jun 2018 22:43:11 -0700 Subject: [PATCH] Update testbenches to use instances() --- example/ATLYS/fpga/tb/test_fpga_core.py | 2 +- example/DE5-Net/fpga/tb/test_fpga_core.py | 2 +- example/HXT100G/fpga/tb/test_fpga_core.py | 9 +-------- example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py | 9 +-------- example/ML605/fpga_gmii/tb/test_fpga_core.py | 2 +- example/ML605/fpga_rgmii/tb/test_fpga_core.py | 2 +- example/ML605/fpga_sgmii/tb/test_fpga_core.py | 2 +- example/NexysVideo/fpga/tb/test_fpga_core.py | 2 +- example/VCU108/fpga_10g/tb/test_fpga_core.py | 2 +- example/VCU108/fpga_1g/tb/test_fpga_core.py | 2 +- example/VCU118/fpga_1g/tb/test_fpga_core.py | 2 +- tb/arp_ep.py | 4 ++-- tb/eth_ep.py | 4 ++-- tb/gmii_ep.py | 4 ++-- tb/ip_ep.py | 4 ++-- tb/rgmii_ep.py | 4 ++-- tb/test_arp.py | 2 +- tb/test_arp_64.py | 2 +- tb/test_arp_cache.py | 2 +- tb/test_arp_eth_rx.py | 2 +- tb/test_arp_eth_rx_64.py | 2 +- tb/test_arp_eth_tx.py | 2 +- tb/test_arp_eth_tx_64.py | 2 +- tb/test_axis_eth_fcs.py | 2 +- tb/test_axis_eth_fcs_64.py | 2 +- tb/test_axis_eth_fcs_check.py | 2 +- tb/test_axis_eth_fcs_check_64.py | 2 +- tb/test_axis_eth_fcs_insert.py | 2 +- tb/test_axis_eth_fcs_insert_64.py | 2 +- tb/test_axis_eth_fcs_insert_64_pad.py | 2 +- tb/test_axis_eth_fcs_insert_pad.py | 2 +- tb/test_axis_gmii_rx.py | 2 +- tb/test_axis_gmii_tx.py | 2 +- tb/test_eth_arb_mux_4.py | 2 +- tb/test_eth_arb_mux_64_4.py | 2 +- tb/test_eth_axis_rx.py | 2 +- tb/test_eth_axis_rx_64.py | 2 +- tb/test_eth_axis_tx.py | 2 +- tb/test_eth_axis_tx_64.py | 2 +- tb/test_eth_demux_4.py | 2 +- tb/test_eth_demux_64_4.py | 2 +- tb/test_eth_mac_10g.py | 2 +- tb/test_eth_mac_10g_fifo.py | 2 +- tb/test_eth_mac_10g_rx.py | 2 +- tb/test_eth_mac_10g_tx.py | 2 +- tb/test_eth_mac_1g.py | 2 +- tb/test_eth_mac_1g_fifo.py | 2 +- tb/test_eth_mac_1g_gmii.py | 2 +- tb/test_eth_mac_1g_gmii_fifo.py | 2 +- tb/test_eth_mac_1g_rgmii.py | 2 +- tb/test_eth_mac_1g_rgmii_fifo.py | 2 +- tb/test_eth_mac_1g_rx.py | 2 +- tb/test_eth_mac_1g_tx.py | 2 +- tb/test_eth_mux_4.py | 2 +- tb/test_eth_mux_64_4.py | 2 +- tb/test_ip.py | 2 +- tb/test_ip_64.py | 2 +- tb/test_ip_arb_mux_4.py | 2 +- tb/test_ip_arb_mux_64_4.py | 2 +- tb/test_ip_complete.py | 2 +- tb/test_ip_complete_64.py | 2 +- tb/test_ip_demux_4.py | 2 +- tb/test_ip_demux_64_4.py | 2 +- tb/test_ip_eth_rx.py | 2 +- tb/test_ip_eth_rx_64.py | 2 +- tb/test_ip_eth_tx.py | 2 +- tb/test_ip_eth_tx_64.py | 2 +- tb/test_ip_mux_4.py | 2 +- tb/test_ip_mux_64_4.py | 2 +- tb/test_udp.py | 2 +- tb/test_udp_64.py | 2 +- tb/test_udp_arb_mux_4.py | 2 +- tb/test_udp_arb_mux_64_4.py | 2 +- tb/test_udp_checksum_gen.py | 2 +- tb/test_udp_checksum_gen_64.py | 2 +- tb/test_udp_complete.py | 2 +- tb/test_udp_complete_64.py | 2 +- tb/test_udp_demux_4.py | 2 +- tb/test_udp_demux_64_4.py | 2 +- tb/test_udp_ip_rx.py | 2 +- tb/test_udp_ip_rx_64.py | 2 +- tb/test_udp_ip_tx.py | 2 +- tb/test_udp_ip_tx_64.py | 2 +- tb/test_udp_mux_4.py | 2 +- tb/test_udp_mux_64_4.py | 2 +- tb/udp_ep.py | 4 ++-- tb/xgmii_ep.py | 4 ++-- 87 files changed, 94 insertions(+), 108 deletions(-) diff --git a/example/ATLYS/fpga/tb/test_fpga_core.py b/example/ATLYS/fpga/tb/test_fpga_core.py index 7cc6dbb3..9a4eaa41 100755 --- a/example/ATLYS/fpga/tb/test_fpga_core.py +++ b/example/ATLYS/fpga/tb/test_fpga_core.py @@ -301,7 +301,7 @@ def bench(): raise StopSimulation - return dut, gmii_source_logic, gmii_sink_logic, clkgen, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/DE5-Net/fpga/tb/test_fpga_core.py b/example/DE5-Net/fpga/tb/test_fpga_core.py index c1eb1506..56ded4c0 100755 --- a/example/DE5-Net/fpga/tb/test_fpga_core.py +++ b/example/DE5-Net/fpga/tb/test_fpga_core.py @@ -293,7 +293,7 @@ def bench(): raise StopSimulation - return dut, sfp_a_source_logic, sfp_a_sink_logic, sfp_b_source_logic, sfp_b_sink_logic, sfp_c_source_logic, sfp_c_sink_logic, sfp_d_source_logic, sfp_d_sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/HXT100G/fpga/tb/test_fpga_core.py b/example/HXT100G/fpga/tb/test_fpga_core.py index 21e9b971..024c6957 100755 --- a/example/HXT100G/fpga/tb/test_fpga_core.py +++ b/example/HXT100G/fpga/tb/test_fpga_core.py @@ -601,14 +601,7 @@ def bench(): raise StopSimulation - return (dut, clkgen, check, eth_r0_source_logic, eth_r0_sink_logic, eth_r1_source_logic, eth_r1_sink_logic, eth_r2_source_logic, eth_r2_sink_logic, - eth_r3_source_logic, eth_r3_sink_logic, eth_r4_source_logic, eth_r4_sink_logic, eth_r5_source_logic, eth_r5_sink_logic, - eth_r6_source_logic, eth_r6_sink_logic, eth_r7_source_logic, eth_r7_sink_logic, eth_r8_source_logic, eth_r8_sink_logic, - eth_r9_source_logic, eth_r9_sink_logic, eth_r10_source_logic, eth_r10_sink_logic, eth_r11_source_logic, eth_r11_sink_logic, - eth_l0_source_logic, eth_l0_sink_logic, eth_l1_source_logic, eth_l1_sink_logic, eth_l2_source_logic, eth_l2_sink_logic, - eth_l3_source_logic, eth_l3_sink_logic, eth_l4_source_logic, eth_l4_sink_logic, eth_l5_source_logic, eth_l5_sink_logic, - eth_l6_source_logic, eth_l6_sink_logic, eth_l7_source_logic, eth_l7_sink_logic, eth_l8_source_logic, eth_l8_sink_logic, - eth_l9_source_logic, eth_l9_sink_logic, eth_l10_source_logic, eth_l10_sink_logic, eth_l11_source_logic, eth_l11_sink_logic) + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py b/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py index 98b82601..b2a1cd1a 100755 --- a/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py +++ b/example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py @@ -533,14 +533,7 @@ def bench(): raise StopSimulation - return (dut, clkgen, check, eth_r0_source_logic, eth_r0_sink_logic, eth_r1_source_logic, eth_r1_sink_logic, eth_r2_source_logic, eth_r2_sink_logic, - eth_r3_source_logic, eth_r3_sink_logic, eth_r4_source_logic, eth_r4_sink_logic, eth_r5_source_logic, eth_r5_sink_logic, - eth_r6_source_logic, eth_r6_sink_logic, eth_r7_source_logic, eth_r7_sink_logic, eth_r8_source_logic, eth_r8_sink_logic, - eth_r9_source_logic, eth_r9_sink_logic, eth_r10_source_logic, eth_r10_sink_logic, eth_r11_source_logic, eth_r11_sink_logic, - eth_l0_source_logic, eth_l0_sink_logic, eth_l1_source_logic, eth_l1_sink_logic, eth_l2_source_logic, eth_l2_sink_logic, - eth_l3_source_logic, eth_l3_sink_logic, eth_l4_source_logic, eth_l4_sink_logic, eth_l5_source_logic, eth_l5_sink_logic, - eth_l6_source_logic, eth_l6_sink_logic, eth_l7_source_logic, eth_l7_sink_logic, eth_l8_source_logic, eth_l8_sink_logic, - eth_l9_source_logic, eth_l9_sink_logic, eth_l10_source_logic, eth_l10_sink_logic, eth_l11_source_logic, eth_l11_sink_logic) + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/ML605/fpga_gmii/tb/test_fpga_core.py b/example/ML605/fpga_gmii/tb/test_fpga_core.py index cfc76965..b4c0cf27 100755 --- a/example/ML605/fpga_gmii/tb/test_fpga_core.py +++ b/example/ML605/fpga_gmii/tb/test_fpga_core.py @@ -320,7 +320,7 @@ def bench(): raise StopSimulation - return dut, gmii_source_logic, gmii_sink_logic, clkgen, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/ML605/fpga_rgmii/tb/test_fpga_core.py b/example/ML605/fpga_rgmii/tb/test_fpga_core.py index 544dc88e..4847fe10 100755 --- a/example/ML605/fpga_rgmii/tb/test_fpga_core.py +++ b/example/ML605/fpga_rgmii/tb/test_fpga_core.py @@ -320,7 +320,7 @@ def bench(): raise StopSimulation - return dut, rgmii_source_logic, rgmii_sink_logic, clkgen, clkgen2, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/ML605/fpga_sgmii/tb/test_fpga_core.py b/example/ML605/fpga_sgmii/tb/test_fpga_core.py index 16c4495e..32db62f3 100755 --- a/example/ML605/fpga_sgmii/tb/test_fpga_core.py +++ b/example/ML605/fpga_sgmii/tb/test_fpga_core.py @@ -317,7 +317,7 @@ def bench(): raise StopSimulation - return dut, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/NexysVideo/fpga/tb/test_fpga_core.py b/example/NexysVideo/fpga/tb/test_fpga_core.py index b0ab838c..b42e78d2 100755 --- a/example/NexysVideo/fpga/tb/test_fpga_core.py +++ b/example/NexysVideo/fpga/tb/test_fpga_core.py @@ -305,7 +305,7 @@ def bench(): raise StopSimulation - return dut, rgmii_source_logic, rgmii_sink_logic, clkgen, clkgen2, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/VCU108/fpga_10g/tb/test_fpga_core.py b/example/VCU108/fpga_10g/tb/test_fpga_core.py index 061c65f3..f16c8cb4 100755 --- a/example/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/example/VCU108/fpga_10g/tb/test_fpga_core.py @@ -511,7 +511,7 @@ def bench(): raise StopSimulation - return dut, qsfp_1_source_logic, qsfp_1_sink_logic, qsfp_2_source_logic, qsfp_2_sink_logic, qsfp_3_source_logic, qsfp_3_sink_logic, qsfp_4_source_logic, qsfp_4_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/VCU108/fpga_1g/tb/test_fpga_core.py b/example/VCU108/fpga_1g/tb/test_fpga_core.py index 0302962b..91a77868 100755 --- a/example/VCU108/fpga_1g/tb/test_fpga_core.py +++ b/example/VCU108/fpga_1g/tb/test_fpga_core.py @@ -304,7 +304,7 @@ def bench(): raise StopSimulation - return dut, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/example/VCU118/fpga_1g/tb/test_fpga_core.py b/example/VCU118/fpga_1g/tb/test_fpga_core.py index 0302962b..91a77868 100755 --- a/example/VCU118/fpga_1g/tb/test_fpga_core.py +++ b/example/VCU118/fpga_1g/tb/test_fpga_core.py @@ -304,7 +304,7 @@ def bench(): raise StopSimulation - return dut, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/arp_ep.py b/tb/arp_ep.py index 9f07516b..9e1eb576 100644 --- a/tb/arp_ep.py +++ b/tb/arp_ep.py @@ -236,7 +236,7 @@ class ARPFrameSource(): frame_valid_int.next = True - return logic, pause_logic + return instances() class ARPFrameSink(): @@ -316,5 +316,5 @@ class ARPFrameSink(): if name is not None: print("[%s] Got frame %s" % (name, repr(frame))) - return logic, pause_logic + return instances() diff --git a/tb/eth_ep.py b/tb/eth_ep.py index 0949454d..89398949 100644 --- a/tb/eth_ep.py +++ b/tb/eth_ep.py @@ -204,7 +204,7 @@ class EthFrameSource(): eth_hdr_valid_int.next = True - return logic, pause_logic, eth_payload_source + return instances() class EthFrameSink(): @@ -295,5 +295,5 @@ class EthFrameSink(): if name is not None: print("[%s] Got frame %s" % (name, repr(frame))) - return logic, pause_logic, eth_payload_sink + return instances() diff --git a/tb/gmii_ep.py b/tb/gmii_ep.py index fb53b2ba..f7beca92 100644 --- a/tb/gmii_ep.py +++ b/tb/gmii_ep.py @@ -172,7 +172,7 @@ class GMIISource(object): tx_er.next = 0 tx_en.next = 0 - return logic + return instances() class GMIISink(object): @@ -261,5 +261,5 @@ class GMIISink(object): d = [] er = [] - return logic + return instances() diff --git a/tb/ip_ep.py b/tb/ip_ep.py index 1f8c4138..26937a9d 100644 --- a/tb/ip_ep.py +++ b/tb/ip_ep.py @@ -356,7 +356,7 @@ class IPFrameSource(): self.header_queue.append(frame) self.payload_source.send(frame.payload) - return logic, pause_logic, ip_payload_source + return instances() class IPFrameSink(): @@ -476,5 +476,5 @@ class IPFrameSink(): if len(self.header_queue) == 0: assert self.payload_sink.empty() - return logic, pause_logic, ip_payload_sink + return instances() diff --git a/tb/rgmii_ep.py b/tb/rgmii_ep.py index 3a46ba0c..705b098c 100644 --- a/tb/rgmii_ep.py +++ b/tb/rgmii_ep.py @@ -63,7 +63,7 @@ class RGMIISource(gmii_ep.GMIISource): gmii_tx_en_reg.next = gmii_tx_en gmii_tx_er_reg.next = gmii_tx_er - return gmii_source, logic + return instances() class RGMIISink(gmii_ep.GMIISink): @@ -102,5 +102,5 @@ class RGMIISink(gmii_ep.GMIISink): dat |= int(rxd.val) << 4 ctl2 = int(rx_ctl.val) - return gmii_sink, logic + return instances() diff --git a/tb/test_arp.py b/tb/test_arp.py index f7d86a53..465bfe63 100755 --- a/tb/test_arp.py +++ b/tb/test_arp.py @@ -435,7 +435,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_arp_64.py b/tb/test_arp_64.py index 2f6c763d..3357ee13 100755 --- a/tb/test_arp_64.py +++ b/tb/test_arp_64.py @@ -441,7 +441,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_arp_cache.py b/tb/test_arp_cache.py index a956d9b0..af268d44 100755 --- a/tb/test_arp_cache.py +++ b/tb/test_arp_cache.py @@ -504,7 +504,7 @@ def bench(): raise StopSimulation - return dut, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_arp_eth_rx.py b/tb/test_arp_eth_rx.py index 64cc9bf1..5641166c 100755 --- a/tb/test_arp_eth_rx.py +++ b/tb/test_arp_eth_rx.py @@ -537,7 +537,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_arp_eth_rx_64.py b/tb/test_arp_eth_rx_64.py index a15b2eef..97bc0ea0 100755 --- a/tb/test_arp_eth_rx_64.py +++ b/tb/test_arp_eth_rx_64.py @@ -540,7 +540,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_arp_eth_tx.py b/tb/test_arp_eth_tx.py index 27ad7c2f..e8751f94 100755 --- a/tb/test_arp_eth_tx.py +++ b/tb/test_arp_eth_tx.py @@ -357,7 +357,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_arp_eth_tx_64.py b/tb/test_arp_eth_tx_64.py index 47e34e74..c8c9a692 100755 --- a/tb/test_arp_eth_tx_64.py +++ b/tb/test_arp_eth_tx_64.py @@ -360,7 +360,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs.py b/tb/test_axis_eth_fcs.py index 4952c827..906a3fb4 100755 --- a/tb/test_axis_eth_fcs.py +++ b/tb/test_axis_eth_fcs.py @@ -145,7 +145,7 @@ def bench(): raise StopSimulation - return dut, source_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs_64.py b/tb/test_axis_eth_fcs_64.py index 8da4ae57..c89e5c9c 100755 --- a/tb/test_axis_eth_fcs_64.py +++ b/tb/test_axis_eth_fcs_64.py @@ -148,7 +148,7 @@ def bench(): raise StopSimulation - return dut, source_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs_check.py b/tb/test_axis_eth_fcs_check.py index 8baec66e..a45f0557 100755 --- a/tb/test_axis_eth_fcs_check.py +++ b/tb/test_axis_eth_fcs_check.py @@ -401,7 +401,7 @@ def bench(): raise StopSimulation - return dut, monitor, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs_check_64.py b/tb/test_axis_eth_fcs_check_64.py index c8fd9a37..9a0e684c 100755 --- a/tb/test_axis_eth_fcs_check_64.py +++ b/tb/test_axis_eth_fcs_check_64.py @@ -407,7 +407,7 @@ def bench(): raise StopSimulation - return dut, monitor, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs_insert.py b/tb/test_axis_eth_fcs_insert.py index 7224cd89..139c1414 100755 --- a/tb/test_axis_eth_fcs_insert.py +++ b/tb/test_axis_eth_fcs_insert.py @@ -368,7 +368,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs_insert_64.py b/tb/test_axis_eth_fcs_insert_64.py index eb0983b0..69abd9d8 100755 --- a/tb/test_axis_eth_fcs_insert_64.py +++ b/tb/test_axis_eth_fcs_insert_64.py @@ -374,7 +374,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs_insert_64_pad.py b/tb/test_axis_eth_fcs_insert_64_pad.py index 4d4ea070..84ce3406 100755 --- a/tb/test_axis_eth_fcs_insert_64_pad.py +++ b/tb/test_axis_eth_fcs_insert_64_pad.py @@ -375,7 +375,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_eth_fcs_insert_pad.py b/tb/test_axis_eth_fcs_insert_pad.py index e9d877a1..aa2123e6 100755 --- a/tb/test_axis_eth_fcs_insert_pad.py +++ b/tb/test_axis_eth_fcs_insert_pad.py @@ -369,7 +369,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_gmii_rx.py b/tb/test_axis_gmii_rx.py index 71e743d0..a94e57df 100755 --- a/tb/test_axis_gmii_rx.py +++ b/tb/test_axis_gmii_rx.py @@ -419,7 +419,7 @@ def bench(): raise StopSimulation - return dut, monitor, source_logic, sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_axis_gmii_tx.py b/tb/test_axis_gmii_tx.py index 89509525..dc3c064f 100755 --- a/tb/test_axis_gmii_tx.py +++ b/tb/test_axis_gmii_tx.py @@ -371,7 +371,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_arb_mux_4.py b/tb/test_eth_arb_mux_4.py index 3a1788e3..f8bf12aa 100755 --- a/tb/test_eth_arb_mux_4.py +++ b/tb/test_eth_arb_mux_4.py @@ -554,7 +554,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_eth_arb_mux_64_4.py b/tb/test_eth_arb_mux_64_4.py index f9125482..ded2000a 100755 --- a/tb/test_eth_arb_mux_64_4.py +++ b/tb/test_eth_arb_mux_64_4.py @@ -569,7 +569,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_eth_axis_rx.py b/tb/test_eth_axis_rx.py index 1901478c..a6af9d50 100755 --- a/tb/test_eth_axis_rx.py +++ b/tb/test_eth_axis_rx.py @@ -346,7 +346,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_axis_rx_64.py b/tb/test_eth_axis_rx_64.py index b1fae272..5eccee57 100755 --- a/tb/test_eth_axis_rx_64.py +++ b/tb/test_eth_axis_rx_64.py @@ -352,7 +352,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_axis_tx.py b/tb/test_eth_axis_tx.py index d19eb90a..254f7ef1 100755 --- a/tb/test_eth_axis_tx.py +++ b/tb/test_eth_axis_tx.py @@ -299,7 +299,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_axis_tx_64.py b/tb/test_eth_axis_tx_64.py index 70e1ed76..332c626d 100755 --- a/tb/test_eth_axis_tx_64.py +++ b/tb/test_eth_axis_tx_64.py @@ -305,7 +305,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_demux_4.py b/tb/test_eth_demux_4.py index 905b5899..36915abb 100755 --- a/tb/test_eth_demux_4.py +++ b/tb/test_eth_demux_4.py @@ -508,7 +508,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_eth_demux_64_4.py b/tb/test_eth_demux_64_4.py index 56ad331a..19f446f1 100755 --- a/tb/test_eth_demux_64_4.py +++ b/tb/test_eth_demux_64_4.py @@ -523,7 +523,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_eth_mac_10g.py b/tb/test_eth_mac_10g.py index 42f8510a..bda37312 100755 --- a/tb/test_eth_mac_10g.py +++ b/tb/test_eth_mac_10g.py @@ -275,7 +275,7 @@ def bench(): raise StopSimulation - return dut, axis_source_logic, axis_sink_logic, xgmii_source_logic, xgmii_sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_10g_fifo.py b/tb/test_eth_mac_10g_fifo.py index 3ff39da6..0194e818 100755 --- a/tb/test_eth_mac_10g_fifo.py +++ b/tb/test_eth_mac_10g_fifo.py @@ -313,7 +313,7 @@ def bench(): raise StopSimulation - return dut, axis_source_logic, axis_sink_logic, xgmii_source_logic, xgmii_sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_10g_rx.py b/tb/test_eth_mac_10g_rx.py index 15a173cf..290fe5d2 100755 --- a/tb/test_eth_mac_10g_rx.py +++ b/tb/test_eth_mac_10g_rx.py @@ -399,7 +399,7 @@ def bench(): raise StopSimulation - return dut, monitor, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_10g_tx.py b/tb/test_eth_mac_10g_tx.py index 665a10a7..06c35d61 100755 --- a/tb/test_eth_mac_10g_tx.py +++ b/tb/test_eth_mac_10g_tx.py @@ -345,7 +345,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g.py b/tb/test_eth_mac_1g.py index 06cf5fe6..8ec11954 100755 --- a/tb/test_eth_mac_1g.py +++ b/tb/test_eth_mac_1g.py @@ -327,7 +327,7 @@ def bench(): raise StopSimulation - return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_fifo.py b/tb/test_eth_mac_1g_fifo.py index b324bf01..2681fde7 100755 --- a/tb/test_eth_mac_1g_fifo.py +++ b/tb/test_eth_mac_1g_fifo.py @@ -358,7 +358,7 @@ def bench(): raise StopSimulation - return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_gmii.py b/tb/test_eth_mac_1g_gmii.py index 088e689c..294cd9ba 100755 --- a/tb/test_eth_mac_1g_gmii.py +++ b/tb/test_eth_mac_1g_gmii.py @@ -331,7 +331,7 @@ def bench(): raise StopSimulation - return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_gmii_fifo.py b/tb/test_eth_mac_1g_gmii_fifo.py index 903d7539..8dda5773 100755 --- a/tb/test_eth_mac_1g_gmii_fifo.py +++ b/tb/test_eth_mac_1g_gmii_fifo.py @@ -355,7 +355,7 @@ def bench(): raise StopSimulation - return dut, monitor, axis_source_logic, axis_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_rgmii.py b/tb/test_eth_mac_1g_rgmii.py index c7fd94f0..e0060c95 100755 --- a/tb/test_eth_mac_1g_rgmii.py +++ b/tb/test_eth_mac_1g_rgmii.py @@ -333,7 +333,7 @@ def bench(): raise StopSimulation - return dut, monitor, axis_source_logic, axis_sink_logic, rgmii_source_logic, rgmii_sink_logic, clkgen, clkgen2, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_rgmii_fifo.py b/tb/test_eth_mac_1g_rgmii_fifo.py index 01d9ec44..111c22f3 100755 --- a/tb/test_eth_mac_1g_rgmii_fifo.py +++ b/tb/test_eth_mac_1g_rgmii_fifo.py @@ -356,7 +356,7 @@ def bench(): raise StopSimulation - return dut, monitor, axis_source_logic, axis_sink_logic, rgmii_source_logic, rgmii_sink_logic, clkgen, clkgen2, rx_clk_gen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_rx.py b/tb/test_eth_mac_1g_rx.py index abf1c088..cfd1c1a0 100755 --- a/tb/test_eth_mac_1g_rx.py +++ b/tb/test_eth_mac_1g_rx.py @@ -366,7 +366,7 @@ def bench(): raise StopSimulation - return dut, monitor, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mac_1g_tx.py b/tb/test_eth_mac_1g_tx.py index 5bda44da..62c3f111 100755 --- a/tb/test_eth_mac_1g_tx.py +++ b/tb/test_eth_mac_1g_tx.py @@ -316,7 +316,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_eth_mux_4.py b/tb/test_eth_mux_4.py index c8adc4b9..d3dd3cfc 100755 --- a/tb/test_eth_mux_4.py +++ b/tb/test_eth_mux_4.py @@ -515,7 +515,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_eth_mux_64_4.py b/tb/test_eth_mux_64_4.py index 61b9860a..8d012851 100755 --- a/tb/test_eth_mux_64_4.py +++ b/tb/test_eth_mux_64_4.py @@ -530,7 +530,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_ip.py b/tb/test_ip.py index 2bc39b5c..fcfdd26f 100755 --- a/tb/test_ip.py +++ b/tb/test_ip.py @@ -524,7 +524,7 @@ def bench(): raise StopSimulation - return dut, eth_source_logic, eth_sink_logic, ip_source_logic, ip_sink_logic, clkgen, arp_emu, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_64.py b/tb/test_ip_64.py index 45000484..a1e5299c 100755 --- a/tb/test_ip_64.py +++ b/tb/test_ip_64.py @@ -536,7 +536,7 @@ def bench(): raise StopSimulation - return dut, eth_source_logic, eth_sink_logic, ip_source_logic, ip_sink_logic, clkgen, arp_emu, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_arb_mux_4.py b/tb/test_ip_arb_mux_4.py index 8418ad7e..54d03d09 100755 --- a/tb/test_ip_arb_mux_4.py +++ b/tb/test_ip_arb_mux_4.py @@ -917,7 +917,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_ip_arb_mux_64_4.py b/tb/test_ip_arb_mux_64_4.py index b1ca7e6d..ea074613 100755 --- a/tb/test_ip_arb_mux_64_4.py +++ b/tb/test_ip_arb_mux_64_4.py @@ -932,7 +932,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_ip_complete.py b/tb/test_ip_complete.py index 12a54e55..1a17adeb 100755 --- a/tb/test_ip_complete.py +++ b/tb/test_ip_complete.py @@ -572,7 +572,7 @@ def bench(): raise StopSimulation - return dut, eth_source_logic, eth_sink_logic, ip_source_logic, ip_sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_complete_64.py b/tb/test_ip_complete_64.py index e2164bd4..0923d771 100755 --- a/tb/test_ip_complete_64.py +++ b/tb/test_ip_complete_64.py @@ -584,7 +584,7 @@ def bench(): raise StopSimulation - return dut, eth_source_logic, eth_sink_logic, ip_source_logic, ip_sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_demux_4.py b/tb/test_ip_demux_4.py index 4016c13f..d3efa6c7 100755 --- a/tb/test_ip_demux_4.py +++ b/tb/test_ip_demux_4.py @@ -843,7 +843,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_ip_demux_64_4.py b/tb/test_ip_demux_64_4.py index 051c833d..7dbed789 100755 --- a/tb/test_ip_demux_64_4.py +++ b/tb/test_ip_demux_64_4.py @@ -858,7 +858,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_ip_eth_rx.py b/tb/test_ip_eth_rx.py index 71d9169c..9cdbed49 100755 --- a/tb/test_ip_eth_rx.py +++ b/tb/test_ip_eth_rx.py @@ -1048,7 +1048,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_eth_rx_64.py b/tb/test_ip_eth_rx_64.py index 3561148f..941af90a 100755 --- a/tb/test_ip_eth_rx_64.py +++ b/tb/test_ip_eth_rx_64.py @@ -1054,7 +1054,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_eth_tx.py b/tb/test_ip_eth_tx.py index fe583645..64f5012a 100755 --- a/tb/test_ip_eth_tx.py +++ b/tb/test_ip_eth_tx.py @@ -849,7 +849,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_eth_tx_64.py b/tb/test_ip_eth_tx_64.py index 3cf9a803..664a0b48 100755 --- a/tb/test_ip_eth_tx_64.py +++ b/tb/test_ip_eth_tx_64.py @@ -855,7 +855,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_ip_mux_4.py b/tb/test_ip_mux_4.py index bea4aa1c..d0feab03 100755 --- a/tb/test_ip_mux_4.py +++ b/tb/test_ip_mux_4.py @@ -850,7 +850,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_ip_mux_64_4.py b/tb/test_ip_mux_64_4.py index 5cd32314..c8509a69 100755 --- a/tb/test_ip_mux_64_4.py +++ b/tb/test_ip_mux_64_4.py @@ -865,7 +865,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_udp.py b/tb/test_udp.py index 584ff07b..a6e395c5 100755 --- a/tb/test_udp.py +++ b/tb/test_udp.py @@ -556,7 +556,7 @@ def bench(): raise StopSimulation - return dut, ip_source_logic, ip_sink_logic, udp_source_logic, udp_sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_64.py b/tb/test_udp_64.py index e9fe9b25..f8d4e75d 100755 --- a/tb/test_udp_64.py +++ b/tb/test_udp_64.py @@ -568,7 +568,7 @@ def bench(): raise StopSimulation - return dut, ip_source_logic, ip_sink_logic, udp_source_logic, udp_sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_arb_mux_4.py b/tb/test_udp_arb_mux_4.py index 96ed5176..4792317e 100755 --- a/tb/test_udp_arb_mux_4.py +++ b/tb/test_udp_arb_mux_4.py @@ -1025,7 +1025,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_udp_arb_mux_64_4.py b/tb/test_udp_arb_mux_64_4.py index b090e0e8..bf9c9dbf 100755 --- a/tb/test_udp_arb_mux_64_4.py +++ b/tb/test_udp_arb_mux_64_4.py @@ -1040,7 +1040,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_udp_checksum_gen.py b/tb/test_udp_checksum_gen.py index 3c30d758..36472b10 100755 --- a/tb/test_udp_checksum_gen.py +++ b/tb/test_udp_checksum_gen.py @@ -493,7 +493,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_checksum_gen_64.py b/tb/test_udp_checksum_gen_64.py index 0fc7a62c..b38633df 100755 --- a/tb/test_udp_checksum_gen_64.py +++ b/tb/test_udp_checksum_gen_64.py @@ -499,7 +499,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_complete.py b/tb/test_udp_complete.py index c4ccad28..d5e880d7 100755 --- a/tb/test_udp_complete.py +++ b/tb/test_udp_complete.py @@ -853,7 +853,7 @@ def bench(): raise StopSimulation - return dut, eth_source_logic, eth_sink_logic, ip_source_logic, ip_sink_logic, udp_source_logic, udp_sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_complete_64.py b/tb/test_udp_complete_64.py index 9da8c1b0..1c01361c 100755 --- a/tb/test_udp_complete_64.py +++ b/tb/test_udp_complete_64.py @@ -871,7 +871,7 @@ def bench(): raise StopSimulation - return dut, eth_source_logic, eth_sink_logic, ip_source_logic, ip_sink_logic, udp_source_logic, udp_sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_demux_4.py b/tb/test_udp_demux_4.py index 6a0a36ec..379a60d6 100755 --- a/tb/test_udp_demux_4.py +++ b/tb/test_udp_demux_4.py @@ -943,7 +943,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_udp_demux_64_4.py b/tb/test_udp_demux_64_4.py index 0060f455..4320d550 100755 --- a/tb/test_udp_demux_64_4.py +++ b/tb/test_udp_demux_64_4.py @@ -958,7 +958,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_0_logic, sink_1_logic, sink_2_logic, sink_3_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_udp_ip_rx.py b/tb/test_udp_ip_rx.py index cbe490c3..f2a7f206 100755 --- a/tb/test_udp_ip_rx.py +++ b/tb/test_udp_ip_rx.py @@ -1034,7 +1034,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_ip_rx_64.py b/tb/test_udp_ip_rx_64.py index 08144b68..dacc540c 100755 --- a/tb/test_udp_ip_rx_64.py +++ b/tb/test_udp_ip_rx_64.py @@ -1040,7 +1040,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_ip_tx.py b/tb/test_udp_ip_tx.py index a5bca5af..c14b6e99 100755 --- a/tb/test_udp_ip_tx.py +++ b/tb/test_udp_ip_tx.py @@ -981,7 +981,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_ip_tx_64.py b/tb/test_udp_ip_tx_64.py index f1a7a701..b6e427cc 100755 --- a/tb/test_udp_ip_tx_64.py +++ b/tb/test_udp_ip_tx_64.py @@ -987,7 +987,7 @@ def bench(): raise StopSimulation - return dut, source_logic, sink_logic, clkgen, monitor, check + return instances() def test_bench(): sim = Simulation(bench()) diff --git a/tb/test_udp_mux_4.py b/tb/test_udp_mux_4.py index 244da968..d6597916 100755 --- a/tb/test_udp_mux_4.py +++ b/tb/test_udp_mux_4.py @@ -950,7 +950,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/test_udp_mux_64_4.py b/tb/test_udp_mux_64_4.py index c1d0b432..cff25d07 100755 --- a/tb/test_udp_mux_64_4.py +++ b/tb/test_udp_mux_64_4.py @@ -965,7 +965,7 @@ def bench(): raise StopSimulation - return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check + return instances() def test_bench(): os.chdir(os.path.dirname(os.path.abspath(__file__))) diff --git a/tb/udp_ep.py b/tb/udp_ep.py index 7d2b87d3..401e1131 100644 --- a/tb/udp_ep.py +++ b/tb/udp_ep.py @@ -449,7 +449,7 @@ class UDPFrameSource(): self.header_queue.append(frame) self.payload_source.send(frame.payload) - return logic, pause_logic, udp_payload_source + return instances() class UDPFrameSink(): @@ -578,5 +578,5 @@ class UDPFrameSink(): if len(self.header_queue) == 0: assert self.payload_sink.empty() - return logic, pause_logic, udp_payload_sink + return instances() diff --git a/tb/xgmii_ep.py b/tb/xgmii_ep.py index adf3f0a1..ca657b15 100644 --- a/tb/xgmii_ep.py +++ b/tb/xgmii_ep.py @@ -225,7 +225,7 @@ class XGMIISource(object): txd.next = 0x0707070707070707 if bw == 8 else 0x07070707 txc.next = 0xff if bw == 8 else 0xf - return logic + return instances() class XGMIISink(object): @@ -307,5 +307,5 @@ class XGMIISink(object): d.append((int(rxd) >> (8*i)) & 0xff) c.append((int(rxc) >> i) & 1) - return logic + return instances()