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Fix FIFO output pause logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2024-01-17 12:17:11 -08:00
parent 7823b916bf
commit e493c6cdb4
2 changed files with 22 additions and 16 deletions
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17
rtl/axis_async_fifo.v
View File

@ -861,18 +861,21 @@ if (PAUSE_ENABLE) begin : pause
always @(posedge m_clk) begin
if (FRAME_PAUSE) begin
if (m_axis_tvalid && m_axis_tready) begin
if (m_axis_tlast) begin
if (pause_reg) begin
// paused; update pause status
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end else if (m_axis_tvalid_out) begin
// frame transfer; set frame bit
pause_frame_reg <= 1'b1;
if (m_axis_tready && m_axis_tlast) begin
// end of frame; clear frame bit and update pause status
pause_frame_reg <= 1'b0;
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end else begin
pause_frame_reg <= 1'b1;
end
end else begin
if (!pause_frame_reg) begin
end else if (!pause_frame_reg) begin
// idle; update pause status
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end
end
end else begin
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end

17
rtl/axis_fifo.v
View File

@ -517,18 +517,21 @@ if (PAUSE_ENABLE) begin : pause
always @(posedge clk) begin
if (FRAME_PAUSE) begin
if (m_axis_tvalid && m_axis_tready) begin
if (m_axis_tlast) begin
if (pause_reg) begin
// paused; update pause status
pause_reg <= pause_req;
end else if (m_axis_tvalid_out) begin
// frame transfer; set frame bit
pause_frame_reg <= 1'b1;
if (m_axis_tready && m_axis_tlast) begin
// end of frame; clear frame bit and update pause status
pause_frame_reg <= 1'b0;
pause_reg <= pause_req;
end else begin
pause_frame_reg <= 1'b1;
end
end else begin
if (!pause_frame_reg) begin
end else if (!pause_frame_reg) begin
// idle; update pause status
pause_reg <= pause_req;
end
end
end else begin
pause_reg <= pause_req;
end