FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity

Add ARP frame to Ethernet frame modules

Browse Source
This commit is contained in:
Alex Forencich 2014-09-15 19:06:02 -07:00
parent d7f30a777b
commit ea2b1b99d0
13 changed files with 4301 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

378
rtl/arp_eth_rx.v Normal file
View File

@ -0,0 +1,378 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* ARP ethernet frame receiver (Ethernet frame in, ARP frame out)
*/
module arp_eth_rx
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [7:0] input_eth_payload_tdata,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* ARP frame output
*/
output wire output_frame_valid,
input wire output_frame_ready,
output wire [47:0] output_eth_dest_mac,
output wire [47:0] output_eth_src_mac,
output wire [15:0] output_eth_type,
output wire [15:0] output_arp_htype,
output wire [15:0] output_arp_ptype,
output wire [7:0] output_arp_hlen,
output wire [7:0] output_arp_plen,
output wire [15:0] output_arp_oper,
output wire [47:0] output_arp_sha,
output wire [31:0] output_arp_spa,
output wire [47:0] output_arp_tha,
output wire [31:0] output_arp_tpa,
/*
* Status signals
*/
output wire busy,
output wire frame_error
);
/*
ARP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0806) 2 octets
HTYPE (1) 2 octets
PTYPE (0x0800) 2 octets
HLEN (6) 1 octets
PLEN (4) 1 octets
OPER 2 octets
SHA Sender MAC 6 octets
SPA Sender IP 4 octets
THA Target MAC 6 octets
TPA Target IP 4 octets
This module receives an Ethernet frame with decoded fields and decodes
the ARP packet format. If the Ethertype does not match, the packet is
discarded.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_WAIT_LAST = 3'd2;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg store_arp_htype_0;
reg store_arp_htype_1;
reg store_arp_ptype_0;
reg store_arp_ptype_1;
reg store_arp_hlen;
reg store_arp_plen;
reg store_arp_oper_0;
reg store_arp_oper_1;
reg store_arp_sha_0;
reg store_arp_sha_1;
reg store_arp_sha_2;
reg store_arp_sha_3;
reg store_arp_sha_4;
reg store_arp_sha_5;
reg store_arp_spa_0;
reg store_arp_spa_1;
reg store_arp_spa_2;
reg store_arp_spa_3;
reg store_arp_tha_0;
reg store_arp_tha_1;
reg store_arp_tha_2;
reg store_arp_tha_3;
reg store_arp_tha_4;
reg store_arp_tha_5;
reg store_arp_tpa_0;
reg store_arp_tpa_1;
reg store_arp_tpa_2;
reg store_arp_tpa_3;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg input_eth_hdr_ready_reg = 0;
reg input_eth_payload_tready_reg = 0;
reg output_frame_valid_reg = 0, output_frame_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [15:0] output_arp_htype_reg = 0;
reg [15:0] output_arp_ptype_reg = 0;
reg [7:0] output_arp_hlen_reg = 0;
reg [7:0] output_arp_plen_reg = 0;
reg [15:0] output_arp_oper_reg = 0;
reg [47:0] output_arp_sha_reg = 0;
reg [31:0] output_arp_spa_reg = 0;
reg [47:0] output_arp_tha_reg = 0;
reg [31:0] output_arp_tpa_reg = 0;
reg busy_reg = 0;
reg frame_error_reg = 0, frame_error_next;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_frame_valid = output_frame_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_arp_htype = output_arp_htype_reg;
assign output_arp_ptype = output_arp_ptype_reg;
assign output_arp_hlen = output_arp_hlen_reg;
assign output_arp_plen = output_arp_plen_reg;
assign output_arp_oper = output_arp_oper_reg;
assign output_arp_sha = output_arp_sha_reg;
assign output_arp_spa = output_arp_spa_reg;
assign output_arp_tha = output_arp_tha_reg;
assign output_arp_tpa = output_arp_tpa_reg;
assign busy = busy_reg;
assign frame_error = frame_error_reg;
always @* begin
state_next = 2'bz;
store_eth_hdr = 0;
store_arp_htype_0 = 0;
store_arp_htype_1 = 0;
store_arp_ptype_0 = 0;
store_arp_ptype_1 = 0;
store_arp_hlen = 0;
store_arp_plen = 0;
store_arp_oper_0 = 0;
store_arp_oper_1 = 0;
store_arp_sha_0 = 0;
store_arp_sha_1 = 0;
store_arp_sha_2 = 0;
store_arp_sha_3 = 0;
store_arp_sha_4 = 0;
store_arp_sha_5 = 0;
store_arp_spa_0 = 0;
store_arp_spa_1 = 0;
store_arp_spa_2 = 0;
store_arp_spa_3 = 0;
store_arp_tha_0 = 0;
store_arp_tha_1 = 0;
store_arp_tha_2 = 0;
store_arp_tha_3 = 0;
store_arp_tha_4 = 0;
store_arp_tha_5 = 0;
store_arp_tpa_0 = 0;
store_arp_tpa_1 = 0;
store_arp_tpa_2 = 0;
store_arp_tpa_3 = 0;
frame_ptr_next = frame_ptr_reg;
output_frame_valid_next = output_frame_valid_reg & ~output_frame_ready;
frame_error_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_eth_hdr_ready & input_eth_hdr_valid) begin
frame_ptr_next = 0;
store_eth_hdr = 1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
if (input_eth_payload_tvalid) begin
// word transfer in - store it
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_READ_HEADER;
case (frame_ptr_reg)
8'h00: store_arp_htype_1 = 1;
8'h01: store_arp_htype_0 = 1;
8'h02: store_arp_ptype_1 = 1;
8'h03: store_arp_ptype_0 = 1;
8'h04: store_arp_hlen = 1;
8'h05: store_arp_plen = 1;
8'h06: store_arp_oper_1 = 1;
8'h07: store_arp_oper_0 = 1;
8'h08: store_arp_sha_5 = 1;
8'h09: store_arp_sha_4 = 1;
8'h0A: store_arp_sha_3 = 1;
8'h0B: store_arp_sha_2 = 1;
8'h0C: store_arp_sha_1 = 1;
8'h0D: store_arp_sha_0 = 1;
8'h0E: store_arp_spa_3 = 1;
8'h0F: store_arp_spa_2 = 1;
8'h10: store_arp_spa_1 = 1;
8'h11: store_arp_spa_0 = 1;
8'h12: store_arp_tha_5 = 1;
8'h13: store_arp_tha_4 = 1;
8'h14: store_arp_tha_3 = 1;
8'h15: store_arp_tha_2 = 1;
8'h16: store_arp_tha_1 = 1;
8'h17: store_arp_tha_0 = 1;
8'h18: store_arp_tpa_3 = 1;
8'h19: store_arp_tpa_2 = 1;
8'h1A: store_arp_tpa_1 = 1;
8'h1B: begin
store_arp_tpa_0 = 1;
output_frame_valid_next = 1;
state_next = STATE_WAIT_LAST;
end
endcase
if (input_eth_payload_tlast) begin
state_next = STATE_IDLE;
if (frame_ptr_reg != 8'h1B) begin
frame_error_next = 1;
end
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_WAIT_LAST: begin
// read last payload word; data in output register; do not accept new data
if (input_eth_payload_tvalid) begin
// word transfer out - done
if (input_eth_payload_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
// wait for end of frame; read and discard
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_frame_valid_reg <= 0;
output_eth_dest_mac_reg <= 0;
output_eth_src_mac_reg <= 0;
output_eth_type_reg <= 0;
busy_reg <= 0;
frame_error_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
output_frame_valid_reg <= output_frame_valid_next;
frame_error_reg <= frame_error_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_eth_hdr_ready_reg <= ~output_frame_valid;
input_eth_payload_tready_reg <= 0;
end
STATE_READ_HEADER: begin
// read header; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
end
endcase
// datapath
if (store_eth_hdr) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
output_eth_src_mac_reg <= input_eth_src_mac;
output_eth_type_reg <= input_eth_type;
end
if (store_arp_htype_0) output_arp_htype_reg[ 7: 0] <= input_eth_payload_tdata;
if (store_arp_htype_1) output_arp_htype_reg[15: 8] <= input_eth_payload_tdata;
if (store_arp_ptype_0) output_arp_ptype_reg[ 7: 0] <= input_eth_payload_tdata;
if (store_arp_ptype_1) output_arp_ptype_reg[15: 8] <= input_eth_payload_tdata;
if (store_arp_hlen) output_arp_hlen_reg <= input_eth_payload_tdata;
if (store_arp_plen) output_arp_plen_reg <= input_eth_payload_tdata;
if (store_arp_oper_0) output_arp_oper_reg[ 7: 0] <= input_eth_payload_tdata;
if (store_arp_oper_1) output_arp_oper_reg[15: 8] <= input_eth_payload_tdata;
if (store_arp_sha_0) output_arp_sha_reg[ 7: 0] <= input_eth_payload_tdata;
if (store_arp_sha_1) output_arp_sha_reg[15: 8] <= input_eth_payload_tdata;
if (store_arp_sha_2) output_arp_sha_reg[23:16] <= input_eth_payload_tdata;
if (store_arp_sha_3) output_arp_sha_reg[31:24] <= input_eth_payload_tdata;
if (store_arp_sha_4) output_arp_sha_reg[39:32] <= input_eth_payload_tdata;
if (store_arp_sha_5) output_arp_sha_reg[47:40] <= input_eth_payload_tdata;
if (store_arp_spa_0) output_arp_spa_reg[ 7: 0] <= input_eth_payload_tdata;
if (store_arp_spa_1) output_arp_spa_reg[15: 8] <= input_eth_payload_tdata;
if (store_arp_spa_2) output_arp_spa_reg[23:16] <= input_eth_payload_tdata;
if (store_arp_spa_3) output_arp_spa_reg[31:24] <= input_eth_payload_tdata;
if (store_arp_tha_0) output_arp_tha_reg[ 7: 0] <= input_eth_payload_tdata;
if (store_arp_tha_1) output_arp_tha_reg[15: 8] <= input_eth_payload_tdata;
if (store_arp_tha_2) output_arp_tha_reg[23:16] <= input_eth_payload_tdata;
if (store_arp_tha_3) output_arp_tha_reg[31:24] <= input_eth_payload_tdata;
if (store_arp_tha_4) output_arp_tha_reg[39:32] <= input_eth_payload_tdata;
if (store_arp_tha_5) output_arp_tha_reg[47:40] <= input_eth_payload_tdata;
if (store_arp_tpa_0) output_arp_tpa_reg[ 7: 0] <= input_eth_payload_tdata;
if (store_arp_tpa_1) output_arp_tpa_reg[15: 8] <= input_eth_payload_tdata;
if (store_arp_tpa_2) output_arp_tpa_reg[23:16] <= input_eth_payload_tdata;
if (store_arp_tpa_3) output_arp_tpa_reg[31:24] <= input_eth_payload_tdata;
end
end
endmodule

315
rtl/arp_eth_rx_64.v Normal file
View File

@ -0,0 +1,315 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* ARP ethernet frame receiver (Ethernet frame in, ARP frame out, 64 bit datapath)
*/
module arp_eth_rx_64
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [63:0] input_eth_payload_tdata,
input wire [7:0] input_eth_payload_tkeep,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* ARP frame output
*/
output wire output_frame_valid,
input wire output_frame_ready,
output wire [47:0] output_eth_dest_mac,
output wire [47:0] output_eth_src_mac,
output wire [15:0] output_eth_type,
output wire [15:0] output_arp_htype,
output wire [15:0] output_arp_ptype,
output wire [7:0] output_arp_hlen,
output wire [7:0] output_arp_plen,
output wire [15:0] output_arp_oper,
output wire [47:0] output_arp_sha,
output wire [31:0] output_arp_spa,
output wire [47:0] output_arp_tha,
output wire [31:0] output_arp_tpa,
/*
* Status signals
*/
output wire busy,
output wire frame_error
);
/*
ARP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0806) 2 octets
HTYPE (1) 2 octets
PTYPE (0x0800) 2 octets
HLEN (6) 1 octets
PLEN (4) 1 octets
OPER 2 octets
SHA Sender MAC 6 octets
SPA Sender IP 4 octets
THA Target MAC 6 octets
TPA Target IP 4 octets
This module receives an Ethernet frame with decoded fields and decodes
the ARP packet format. If the Ethertype does not match, the packet is
discarded.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_WAIT_LAST = 3'd2;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg store_arp_hdr_word_0;
reg store_arp_hdr_word_1;
reg store_arp_hdr_word_2;
reg store_arp_hdr_word_3;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg input_eth_hdr_ready_reg = 0;
reg input_eth_payload_tready_reg = 0;
reg output_frame_valid_reg = 0, output_frame_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [15:0] output_arp_htype_reg = 0;
reg [15:0] output_arp_ptype_reg = 0;
reg [7:0] output_arp_hlen_reg = 0;
reg [7:0] output_arp_plen_reg = 0;
reg [15:0] output_arp_oper_reg = 0;
reg [47:0] output_arp_sha_reg = 0;
reg [31:0] output_arp_spa_reg = 0;
reg [47:0] output_arp_tha_reg = 0;
reg [31:0] output_arp_tpa_reg = 0;
reg busy_reg = 0;
reg frame_error_reg = 0, frame_error_next;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_frame_valid = output_frame_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_arp_htype = output_arp_htype_reg;
assign output_arp_ptype = output_arp_ptype_reg;
assign output_arp_hlen = output_arp_hlen_reg;
assign output_arp_plen = output_arp_plen_reg;
assign output_arp_oper = output_arp_oper_reg;
assign output_arp_sha = output_arp_sha_reg;
assign output_arp_spa = output_arp_spa_reg;
assign output_arp_tha = output_arp_tha_reg;
assign output_arp_tpa = output_arp_tpa_reg;
assign busy = busy_reg;
assign frame_error = frame_error_reg;
always @* begin
state_next = 2'bz;
store_eth_hdr = 0;
store_arp_hdr_word_0 = 0;
store_arp_hdr_word_1 = 0;
store_arp_hdr_word_2 = 0;
store_arp_hdr_word_3 = 0;
frame_ptr_next = frame_ptr_reg;
output_frame_valid_next = output_frame_valid_reg & ~output_frame_ready;
frame_error_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_eth_hdr_ready & input_eth_hdr_valid) begin
frame_ptr_next = 0;
store_eth_hdr = 1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
if (input_eth_payload_tvalid) begin
// word transfer in - store it
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_READ_HEADER;
case (frame_ptr_reg)
8'h00: store_arp_hdr_word_0 = 1;
8'h01: store_arp_hdr_word_1 = 1;
8'h02: store_arp_hdr_word_2 = 1;
8'h03: begin
store_arp_hdr_word_3 = 1;
output_frame_valid_next = 1;
state_next = STATE_WAIT_LAST;
end
endcase
if (input_eth_payload_tlast) begin
state_next = STATE_IDLE;
if (frame_ptr_reg != 8'h03 | (input_eth_payload_tkeep & 8'h0F) != 8'h0F) begin
frame_error_next = 1;
end
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_WAIT_LAST: begin
// read last payload word; data in output register; do not accept new data
if (input_eth_payload_tvalid) begin
// word transfer out - done
if (input_eth_payload_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
// wait for end of frame; read and discard
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_frame_valid_reg <= 0;
output_eth_dest_mac_reg <= 0;
output_eth_src_mac_reg <= 0;
output_eth_type_reg <= 0;
busy_reg <= 0;
frame_error_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
output_frame_valid_reg <= output_frame_valid_next;
frame_error_reg <= frame_error_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_eth_hdr_ready_reg <= ~output_frame_valid;
input_eth_payload_tready_reg <= 0;
end
STATE_READ_HEADER: begin
// read header; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
end
endcase
// datapath
if (store_eth_hdr) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
output_eth_src_mac_reg <= input_eth_src_mac;
output_eth_type_reg <= input_eth_type;
end
if (store_arp_hdr_word_0) begin
output_arp_htype_reg[15: 8] <= input_eth_payload_tdata[ 7: 0];
output_arp_htype_reg[ 7: 0] <= input_eth_payload_tdata[15: 8];
output_arp_ptype_reg[15: 8] <= input_eth_payload_tdata[23:16];
output_arp_ptype_reg[ 7: 0] <= input_eth_payload_tdata[31:24];
output_arp_hlen_reg <= input_eth_payload_tdata[39:32];
output_arp_plen_reg <= input_eth_payload_tdata[47:40];
output_arp_oper_reg[15: 8] <= input_eth_payload_tdata[55:48];
output_arp_oper_reg[ 7: 0] <= input_eth_payload_tdata[63:56];
end
if (store_arp_hdr_word_1) begin
output_arp_sha_reg[47:40] <= input_eth_payload_tdata[ 7: 0];
output_arp_sha_reg[39:32] <= input_eth_payload_tdata[15: 8];
output_arp_sha_reg[31:24] <= input_eth_payload_tdata[23:16];
output_arp_sha_reg[23:16] <= input_eth_payload_tdata[31:24];
output_arp_sha_reg[15: 8] <= input_eth_payload_tdata[39:32];
output_arp_sha_reg[ 7: 0] <= input_eth_payload_tdata[47:40];
output_arp_spa_reg[31:24] <= input_eth_payload_tdata[55:48];
output_arp_spa_reg[23:16] <= input_eth_payload_tdata[63:56];
end
if (store_arp_hdr_word_2) begin
output_arp_spa_reg[15: 8] <= input_eth_payload_tdata[ 7: 0];
output_arp_spa_reg[ 7: 0] <= input_eth_payload_tdata[15: 8];
output_arp_tha_reg[47:40] <= input_eth_payload_tdata[23:16];
output_arp_tha_reg[39:32] <= input_eth_payload_tdata[31:24];
output_arp_tha_reg[31:24] <= input_eth_payload_tdata[39:32];
output_arp_tha_reg[23:16] <= input_eth_payload_tdata[47:40];
output_arp_tha_reg[15: 8] <= input_eth_payload_tdata[55:48];
output_arp_tha_reg[ 7: 0] <= input_eth_payload_tdata[63:56];
end
if (store_arp_hdr_word_3) begin
output_arp_tpa_reg[31:24] <= input_eth_payload_tdata[ 7: 0];
output_arp_tpa_reg[23:16] <= input_eth_payload_tdata[15: 8];
output_arp_tpa_reg[15: 8] <= input_eth_payload_tdata[23:16];
output_arp_tpa_reg[ 7: 0] <= input_eth_payload_tdata[31:24];
end
end
end
endmodule

309
rtl/arp_eth_tx.v Normal file
View File

@ -0,0 +1,309 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* ARP ethernet frame transmitter (ARP frame in, Ethernet frame out)
*/
module arp_eth_tx
(
input wire clk,
input wire rst,
/*
* ARP frame input
*/
input wire input_frame_valid,
output wire input_frame_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [15:0] input_arp_htype,
input wire [15:0] input_arp_ptype,
input wire [7:0] input_arp_hlen,
input wire [7:0] input_arp_plen,
input wire [15:0] input_arp_oper,
input wire [47:0] input_arp_sha,
input wire [31:0] input_arp_spa,
input wire [47:0] input_arp_tha,
input wire [31:0] input_arp_tpa,
/*
* Ethernet frame output
*/
output wire output_eth_hdr_valid,
input wire output_eth_hdr_ready,
output wire [47:0] output_eth_dest_mac,
output wire [47:0] output_eth_src_mac,
output wire [15:0] output_eth_type,
output wire [7:0] output_eth_payload_tdata,
output wire output_eth_payload_tvalid,
input wire output_eth_payload_tready,
output wire output_eth_payload_tlast,
output wire output_eth_payload_tuser,
/*
* Status signals
*/
output wire busy
);
/*
ARP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0806) 2 octets
HTYPE (1) 2 octets
PTYPE (0x0800) 2 octets
HLEN (6) 1 octets
PLEN (4) 1 octets
OPER 2 octets
SHA Sender MAC 6 octets
SPA Sender IP 4 octets
THA Target MAC 6 octets
TPA Target IP 4 octets
This module receives an Ethernet frame with decoded fields and decodes
the ARP packet format. If the Ethertype does not match, the packet is
discarded.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_HEADER_LAST = 3'd2;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_frame;
reg [7:0] write_hdr_data;
reg write_hdr_last;
reg write_hdr_out;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg [47:0] output_eth_dest_mac_reg = 0;
reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [15:0] arp_htype_reg = 0;
reg [15:0] arp_ptype_reg = 0;
reg [7:0] arp_hlen_reg = 0;
reg [7:0] arp_plen_reg = 0;
reg [15:0] arp_oper_reg = 0;
reg [47:0] arp_sha_reg = 0;
reg [31:0] arp_spa_reg = 0;
reg [47:0] arp_tha_reg = 0;
reg [31:0] arp_tpa_reg = 0;
reg input_frame_ready_reg = 0;
reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next;
reg [7:0] output_eth_payload_tdata_reg = 0;
reg output_eth_payload_tvalid_reg = 0;
reg output_eth_payload_tlast_reg = 0;
reg output_eth_payload_tuser_reg = 0;
reg busy_reg = 0;
assign input_frame_ready = input_frame_ready_reg;
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
assign busy = busy_reg;
always @* begin
state_next = 2'bz;
store_frame = 0;
write_hdr_data = 0;
write_hdr_last = 0;
write_hdr_out = 0;
frame_ptr_next = frame_ptr_reg;
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_frame_valid) begin
store_frame = 1;
write_hdr_out = 1;
write_hdr_data = input_arp_htype[15: 8];
output_eth_hdr_valid_next = 1;
frame_ptr_next = 1;
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// read header state
if (output_eth_payload_tready) begin
// word transfer out
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_WRITE_HEADER;
write_hdr_out = 1;
case (frame_ptr_reg)
8'h01: write_hdr_data = arp_htype_reg[ 7: 0];
8'h02: write_hdr_data = arp_ptype_reg[15: 8];
8'h03: write_hdr_data = arp_ptype_reg[ 7: 0];
8'h04: write_hdr_data = arp_hlen_reg;
8'h05: write_hdr_data = arp_plen_reg;
8'h06: write_hdr_data = arp_oper_reg[15: 8];
8'h07: write_hdr_data = arp_oper_reg[ 7: 0];
8'h08: write_hdr_data = arp_sha_reg[47:40];
8'h09: write_hdr_data = arp_sha_reg[39:32];
8'h0A: write_hdr_data = arp_sha_reg[31:24];
8'h0B: write_hdr_data = arp_sha_reg[23:16];
8'h0C: write_hdr_data = arp_sha_reg[15: 8];
8'h0D: write_hdr_data = arp_sha_reg[ 7: 0];
8'h0E: write_hdr_data = arp_spa_reg[31:24];
8'h0F: write_hdr_data = arp_spa_reg[23:16];
8'h10: write_hdr_data = arp_spa_reg[15: 8];
8'h11: write_hdr_data = arp_spa_reg[ 7: 0];
8'h12: write_hdr_data = arp_tha_reg[47:40];
8'h13: write_hdr_data = arp_tha_reg[39:32];
8'h14: write_hdr_data = arp_tha_reg[31:24];
8'h15: write_hdr_data = arp_tha_reg[23:16];
8'h16: write_hdr_data = arp_tha_reg[15: 8];
8'h17: write_hdr_data = arp_tha_reg[ 7: 0];
8'h18: write_hdr_data = arp_tpa_reg[31:24];
8'h19: write_hdr_data = arp_tpa_reg[23:16];
8'h1A: write_hdr_data = arp_tpa_reg[15: 8];
8'h1B: begin
write_hdr_data = arp_tpa_reg[ 7: 0];
write_hdr_last = 1;
state_next = STATE_WRITE_HEADER_LAST;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_HEADER_LAST: begin
// write last header word; data in output register
if (output_eth_payload_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_HEADER_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_frame_ready_reg <= 0;
output_eth_dest_mac_reg <= 0;
output_eth_src_mac_reg <= 0;
output_eth_type_reg <= 0;
arp_htype_reg <= 0;
arp_ptype_reg <= 0;
arp_hlen_reg <= 0;
arp_plen_reg <= 0;
arp_oper_reg <= 0;
arp_sha_reg <= 0;
arp_spa_reg <= 0;
arp_tha_reg <= 0;
arp_tpa_reg <= 0;
output_eth_payload_tdata_reg <= 0;
output_eth_payload_tvalid_reg <= 0;
output_eth_payload_tlast_reg <= 0;
output_eth_payload_tuser_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_frame_ready_reg <= ~output_eth_hdr_valid;
output_eth_payload_tvalid_reg <= 0;
end
STATE_WRITE_HEADER: begin
// write header
input_frame_ready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
STATE_WRITE_HEADER_LAST: begin
// write last header word; data in output register
input_frame_ready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
endcase
if (store_frame) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
output_eth_src_mac_reg <= input_eth_src_mac;
output_eth_type_reg <= input_eth_type;
arp_htype_reg <= input_arp_htype;
arp_ptype_reg <= input_arp_ptype;
arp_hlen_reg <= input_arp_hlen;
arp_plen_reg <= input_arp_plen;
arp_oper_reg <= input_arp_oper;
arp_sha_reg <= input_arp_sha;
arp_spa_reg <= input_arp_spa;
arp_tha_reg <= input_arp_tha;
arp_tpa_reg <= input_arp_tpa;
end
if (write_hdr_out) begin
output_eth_payload_tdata_reg <= write_hdr_data;
output_eth_payload_tlast_reg <= write_hdr_last;
output_eth_payload_tuser_reg <= 0;
end
end
end
endmodule

328
rtl/arp_eth_tx_64.v Normal file
View File

@ -0,0 +1,328 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* ARP ethernet frame transmitter (ARP frame in, Ethernet frame out, 64 bit datapath)
*/
module arp_eth_tx_64
(
input wire clk,
input wire rst,
/*
* ARP frame input
*/
input wire input_frame_valid,
output wire input_frame_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [15:0] input_arp_htype,
input wire [15:0] input_arp_ptype,
input wire [7:0] input_arp_hlen,
input wire [7:0] input_arp_plen,
input wire [15:0] input_arp_oper,
input wire [47:0] input_arp_sha,
input wire [31:0] input_arp_spa,
input wire [47:0] input_arp_tha,
input wire [31:0] input_arp_tpa,
/*
* Ethernet frame output
*/
output wire output_eth_hdr_valid,
input wire output_eth_hdr_ready,
output wire [47:0] output_eth_dest_mac,
output wire [47:0] output_eth_src_mac,
output wire [15:0] output_eth_type,
output wire [63:0] output_eth_payload_tdata,
output wire [7:0] output_eth_payload_tkeep,
output wire output_eth_payload_tvalid,
input wire output_eth_payload_tready,
output wire output_eth_payload_tlast,
output wire output_eth_payload_tuser,
/*
* Status signals
*/
output wire busy
);
/*
ARP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0806) 2 octets
HTYPE (1) 2 octets
PTYPE (0x0800) 2 octets
HLEN (6) 1 octets
PLEN (4) 1 octets
OPER 2 octets
SHA Sender MAC 6 octets
SPA Sender IP 4 octets
THA Target MAC 6 octets
TPA Target IP 4 octets
This module receives an Ethernet frame with decoded fields and decodes
the ARP packet format. If the Ethertype does not match, the packet is
discarded.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_HEADER_LAST = 3'd2;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_frame;
reg [63:0] write_hdr_data;
reg [7:0] write_hdr_keep;
reg write_hdr_last;
reg write_hdr_out;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg [47:0] output_eth_dest_mac_reg = 0;
reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [15:0] arp_htype_reg = 0;
reg [15:0] arp_ptype_reg = 0;
reg [7:0] arp_hlen_reg = 0;
reg [7:0] arp_plen_reg = 0;
reg [15:0] arp_oper_reg = 0;
reg [47:0] arp_sha_reg = 0;
reg [31:0] arp_spa_reg = 0;
reg [47:0] arp_tha_reg = 0;
reg [31:0] arp_tpa_reg = 0;
reg input_frame_ready_reg = 0;
reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next;
reg [63:0] output_eth_payload_tdata_reg = 0;
reg [7:0] output_eth_payload_tkeep_reg = 0;
reg output_eth_payload_tvalid_reg = 0;
reg output_eth_payload_tlast_reg = 0;
reg output_eth_payload_tuser_reg = 0;
reg busy_reg = 0;
assign input_frame_ready = input_frame_ready_reg;
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg;
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
assign busy = busy_reg;
always @* begin
state_next = 2'bz;
store_frame = 0;
write_hdr_data = 0;
write_hdr_keep = 0;
write_hdr_last = 0;
write_hdr_out = 0;
frame_ptr_next = frame_ptr_reg;
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_frame_valid) begin
store_frame = 1;
write_hdr_out = 1;
write_hdr_data[ 7: 0] = input_arp_htype[15: 8];
write_hdr_data[15: 8] = input_arp_htype[ 7: 0];
write_hdr_data[23:16] = input_arp_ptype[15: 8];
write_hdr_data[31:24] = input_arp_ptype[ 7: 0];
write_hdr_data[39:32] = input_arp_hlen;
write_hdr_data[47:40] = input_arp_plen;
write_hdr_data[55:48] = input_arp_oper[15: 8];
write_hdr_data[63:56] = input_arp_oper[ 7: 0];
write_hdr_keep = 8'hff;
frame_ptr_next = 8;
output_eth_hdr_valid_next = 1;
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// read header state
if (output_eth_payload_tready) begin
// word transfer out
frame_ptr_next = frame_ptr_reg+8;
state_next = STATE_WRITE_HEADER;
write_hdr_out = 1;
case (frame_ptr_reg)
8'h08: begin
write_hdr_data[ 7: 0] = arp_sha_reg[47:40];
write_hdr_data[15: 8] = arp_sha_reg[39:32];
write_hdr_data[23:16] = arp_sha_reg[31:24];
write_hdr_data[31:24] = arp_sha_reg[23:16];
write_hdr_data[39:32] = arp_sha_reg[15: 8];
write_hdr_data[47:40] = arp_sha_reg[ 7: 0];
write_hdr_data[55:48] = arp_spa_reg[31:24];
write_hdr_data[63:56] = arp_spa_reg[23:16];
write_hdr_keep = 8'hff;
end
8'h10: begin
write_hdr_data[ 7: 0] = arp_spa_reg[15: 8];
write_hdr_data[15: 8] = arp_spa_reg[ 7: 0];
write_hdr_data[23:16] = arp_tha_reg[47:40];
write_hdr_data[31:24] = arp_tha_reg[39:32];
write_hdr_data[39:32] = arp_tha_reg[31:24];
write_hdr_data[47:40] = arp_tha_reg[23:16];
write_hdr_data[55:48] = arp_tha_reg[15: 8];
write_hdr_data[63:56] = arp_tha_reg[ 7: 0];
write_hdr_keep = 8'hff;
end
8'h18: begin
write_hdr_data[ 7: 0] = arp_tpa_reg[31:24];
write_hdr_data[15: 8] = arp_tpa_reg[23:16];
write_hdr_data[23:16] = arp_tpa_reg[15: 8];
write_hdr_data[31:24] = arp_tpa_reg[ 7: 0];
write_hdr_data[39:32] = 0;
write_hdr_data[47:40] = 0;
write_hdr_data[55:48] = 0;
write_hdr_data[63:56] = 0;
write_hdr_keep = 8'h0f;
write_hdr_last = 1;
state_next = STATE_WRITE_HEADER_LAST;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_HEADER_LAST: begin
// write last header word; data in output register
if (output_eth_payload_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_HEADER_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_frame_ready_reg <= 0;
output_eth_dest_mac_reg <= 0;
output_eth_src_mac_reg <= 0;
output_eth_type_reg <= 0;
arp_htype_reg <= 0;
arp_ptype_reg <= 0;
arp_hlen_reg <= 0;
arp_plen_reg <= 0;
arp_oper_reg <= 0;
arp_sha_reg <= 0;
arp_spa_reg <= 0;
arp_tha_reg <= 0;
arp_tpa_reg <= 0;
output_eth_payload_tdata_reg <= 0;
output_eth_payload_tkeep_reg <= 0;
output_eth_payload_tvalid_reg <= 0;
output_eth_payload_tlast_reg <= 0;
output_eth_payload_tuser_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_frame_ready_reg <= ~output_eth_hdr_valid;
output_eth_payload_tvalid_reg <= 0;
end
STATE_WRITE_HEADER: begin
// write header
input_frame_ready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
STATE_WRITE_HEADER_LAST: begin
// write last header word; data in output register
input_frame_ready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
endcase
if (store_frame) begin
output_eth_dest_mac_reg <= input_eth_dest_mac;
output_eth_src_mac_reg <= input_eth_src_mac;
output_eth_type_reg <= input_eth_type;
arp_htype_reg <= input_arp_htype;
arp_ptype_reg <= input_arp_ptype;
arp_hlen_reg <= input_arp_hlen;
arp_plen_reg <= input_arp_plen;
arp_oper_reg <= input_arp_oper;
arp_sha_reg <= input_arp_sha;
arp_spa_reg <= input_arp_spa;
arp_tha_reg <= input_arp_tha;
arp_tpa_reg <= input_arp_tpa;
end
if (write_hdr_out) begin
output_eth_payload_tdata_reg <= write_hdr_data;
output_eth_payload_tkeep_reg <= write_hdr_keep;
output_eth_payload_tlast_reg <= write_hdr_last;
output_eth_payload_tuser_reg <= 0;
end
end
end
endmodule

279
tb/arp_ep.py Normal file
View File

@ -0,0 +1,279 @@
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import axis_ep
import eth_ep
from Queue import Queue
import struct
class ARPFrame(object):
def __init__(self,
eth_dest_mac=0,
eth_src_mac=0,
eth_type=0,
arp_htype=1,
arp_ptype=0x0800,
arp_hlen=6,
arp_plen=4,
arp_oper=2,
arp_sha=0x5A5152535455,
arp_spa=0xc0a80164,
arp_tha=0xDAD1D2D3D4D5,
arp_tpa=0xc0a80164):
self.eth_dest_mac = eth_dest_mac
self.eth_src_mac = eth_src_mac
self.eth_type = eth_type
self.arp_htype = arp_htype
self.arp_ptype = arp_ptype
self.arp_hlen = arp_hlen
self.arp_plen = arp_plen
self.arp_oper = arp_oper
self.arp_sha = arp_sha
self.arp_spa = arp_spa
self.arp_tha = arp_tha
self.arp_tpa = arp_tpa
if type(eth_dest_mac) is dict:
self.eth_dest_mac = eth_dest_mac['eth_dest_mac']
self.eth_src_mac = eth_dest_mac['eth_src_mac']
self.eth_type = eth_dest_mac['eth_type']
self.arp_htype = eth_dest_mac['arp_htype']
self.arp_ptype = eth_dest_mac['arp_ptype']
self.arp_hlen = eth_dest_mac['arp_hlen']
self.arp_plen = eth_dest_mac['arp_plen']
self.arp_oper = eth_dest_mac['arp_oper']
self.arp_sha = eth_dest_mac['arp_sha']
self.arp_spa = eth_dest_mac['arp_spa']
self.arp_tha = eth_dest_mac['arp_tha']
self.arp_tpa = eth_dest_mac['arp_tpa']
if type(eth_dest_mac) is ARPFrame:
self.eth_dest_mac = eth_dest_mac.eth_dest_mac
self.eth_src_mac = eth_dest_mac.eth_src_mac
self.eth_type = eth_dest_mac.eth_type
self.arp_htype = eth_dest_mac.arp_htype
self.arp_ptype = eth_dest_mac.arp_ptype
self.arp_hlen = eth_dest_mac.arp_hlen
self.arp_plen = eth_dest_mac.arp_plen
self.arp_oper = eth_dest_mac.arp_oper
self.arp_sha = eth_dest_mac.arp_sha
self.arp_spa = eth_dest_mac.arp_spa
self.arp_tha = eth_dest_mac.arp_tha
self.arp_tpa = eth_dest_mac.arp_tpa
def build_axis(self):
return self.build_eth().build_axis()
def build_eth(self):
data = b''
data += struct.pack('>H', self.arp_htype)
data += struct.pack('>H', self.arp_ptype)
data += struct.pack('B', self.arp_hlen)
data += struct.pack('B', self.arp_plen)
data += struct.pack('>H', self.arp_oper)
data += struct.pack('>Q', self.arp_sha)[2:]
data += struct.pack('>L', self.arp_spa)
data += struct.pack('>Q', self.arp_tha)[2:]
data += struct.pack('>L', self.arp_tpa)
return eth_ep.EthFrame(data, self.eth_dest_mac, self.eth_src_mac, self.eth_type)
def parse_axis(self, data):
frame = eth_ep.EthFrame()
frame.parse_axis(data)
self.parse_eth(frame)
def parse_eth(self, data):
self.eth_src_mac = data.eth_src_mac
self.eth_dest_mac = data.eth_dest_mac
self.eth_type = data.eth_type
self.arp_htype = struct.unpack('>H', data.payload.data[0:2])[0]
self.arp_ptype = struct.unpack('>H', data.payload.data[2:4])[0]
self.arp_hlen = struct.unpack('B', data.payload.data[4:5])[0]
self.arp_plen = struct.unpack('B', data.payload.data[5:6])[0]
self.arp_oper = struct.unpack('>H', data.payload.data[6:8])[0]
self.arp_sha = struct.unpack('>Q', '\x00\x00'+data.payload.data[8:14])[0]
self.arp_spa = struct.unpack('>L', data.payload.data[14:18])[0]
self.arp_tha = struct.unpack('>Q', '\x00\x00'+data.payload.data[18:24])[0]
self.arp_tpa = struct.unpack('>L', data.payload.data[24:28])[0]
def __eq__(self, other):
if type(other) is ARPFrame:
return (self.eth_src_mac == other.eth_src_mac and
self.eth_dest_mac == other.eth_dest_mac and
self.eth_type == other.eth_type and
self.arp_htype == other.arp_htype and
self.arp_ptype == other.arp_ptype and
self.arp_hlen == other.arp_hlen and
self.arp_plen == other.arp_plen and
self.arp_oper == other.arp_oper and
self.arp_sha == other.arp_sha and
self.arp_spa == other.arp_spa and
self.arp_tha == other.arp_tha and
self.arp_tpa == other.arp_tpa)
def __repr__(self):
return (('ArpFrame(eth_dest_mac=0x%012x, ' % self.eth_dest_mac) +
('eth_src_mac=0x%012x, ' % self.eth_src_mac) +
('eth_type=0x%04x, ' % self.eth_type) +
('arp_htype=0x%04x, ' % self.arp_htype) +
('arp_ptype=0x%04x, ' % self.arp_ptype) +
('arp_hlen=%d, ' % self.arp_hlen) +
('arp_plen=%d, ' % self.arp_plen) +
('arp_oper=0x%04x, ' % self.arp_oper) +
('arp_sha=0x%012x, ' % self.arp_sha) +
('arp_spa=0x%08x, ' % self.arp_spa) +
('arp_tha=0x%012x, ' % self.arp_tha) +
('arp_tpa=0x%08x)' % self.arp_tpa))
def ARPFrameSource(clk, rst,
frame_valid=None,
frame_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
arp_htype=None,
arp_ptype=None,
arp_hlen=None,
arp_plen=None,
arp_oper=None,
arp_sha=None,
arp_spa=None,
arp_tha=None,
arp_tpa=None,
fifo=None,
pause=0,
name=None):
frame_ready_int = Signal(bool(False))
frame_valid_int = Signal(bool(False))
@always_comb
def pause_logic():
frame_ready_int.next = frame_ready and not pause
frame_valid.next = frame_valid_int and not pause
@instance
def logic():
frame = dict()
while True:
yield clk.posedge, rst.posedge
if rst:
frame_valid_int.next = False
else:
if frame_ready_int:
frame_valid_int.next = False
if (frame_ready_int and frame_valid) or not frame_valid_int:
if not fifo.empty():
frame = fifo.get()
frame = ARPFrame(frame)
eth_dest_mac.next = frame.eth_dest_mac
eth_src_mac.next = frame.eth_src_mac
eth_type.next = frame.eth_type
arp_htype.next = frame.arp_htype
arp_ptype.next = frame.arp_ptype
arp_hlen.next = frame.arp_hlen
arp_plen.next = frame.arp_plen
arp_oper.next = frame.arp_oper
arp_sha.next = frame.arp_sha
arp_spa.next = frame.arp_spa
arp_tha.next = frame.arp_tha
arp_tpa.next = frame.arp_tpa
if name is not None:
print("[%s] Sending frame %s" % (name, repr(frame)))
frame_valid_int.next = True
return logic, pause_logic
def ARPFrameSink(clk, rst,
frame_valid=None,
frame_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
arp_htype=None,
arp_ptype=None,
arp_hlen=None,
arp_plen=None,
arp_oper=None,
arp_sha=None,
arp_spa=None,
arp_tha=None,
arp_tpa=None,
fifo=None,
pause=0,
name=None):
frame_ready_int = Signal(bool(False))
frame_valid_int = Signal(bool(False))
@always_comb
def pause_logic():
frame_ready.next = frame_ready_int and not pause
frame_valid_int.next = frame_valid and not pause
@instance
def logic():
frame = ARPFrame()
while True:
yield clk.posedge, rst.posedge
if rst:
frame_ready_int.next = False
frame = ARPFrame()
else:
frame_ready_int.next = True
if frame_ready_int and frame_valid_int:
frame = ARPFrame()
frame.eth_dest_mac = int(eth_dest_mac)
frame.eth_src_mac = int(eth_src_mac)
frame.eth_type = int(eth_type)
frame.arp_htype = int(arp_htype)
frame.arp_ptype = int(arp_ptype)
frame.arp_hlen = int(arp_hlen)
frame.arp_plen = int(arp_plen)
frame.arp_oper = int(arp_oper)
frame.arp_sha = int(arp_sha)
frame.arp_spa = int(arp_spa)
frame.arp_tha = int(arp_tha)
frame.arp_tpa = int(arp_tpa)
fifo.put(frame)
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))
frame = dict()
return logic, pause_logic

595
tb/test_arp_eth_rx.py Executable file
View File

@ -0,0 +1,595 @@
#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import arp_ep
import eth_ep
module = 'arp_eth_rx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arp_eth_rx(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_frame_valid,
output_frame_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_arp_htype,
output_arp_ptype,
output_arp_hlen,
output_arp_plen,
output_arp_oper,
output_arp_sha,
output_arp_spa,
output_arp_tha,
output_arp_tpa,
busy,
frame_error):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_eth_hdr_valid=input_eth_hdr_valid,
input_eth_hdr_ready=input_eth_hdr_ready,
input_eth_dest_mac=input_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac,
input_eth_type=input_eth_type,
input_eth_payload_tdata=input_eth_payload_tdata,
input_eth_payload_tvalid=input_eth_payload_tvalid,
input_eth_payload_tready=input_eth_payload_tready,
input_eth_payload_tlast=input_eth_payload_tlast,
input_eth_payload_tuser=input_eth_payload_tuser,
output_frame_valid=output_frame_valid,
output_frame_ready=output_frame_ready,
output_eth_dest_mac=output_eth_dest_mac,
output_eth_src_mac=output_eth_src_mac,
output_eth_type=output_eth_type,
output_arp_htype=output_arp_htype,
output_arp_ptype=output_arp_ptype,
output_arp_hlen=output_arp_hlen,
output_arp_plen=output_arp_plen,
output_arp_oper=output_arp_oper,
output_arp_sha=output_arp_sha,
output_arp_spa=output_arp_spa,
output_arp_tha=output_arp_tha,
output_arp_tpa=output_arp_tpa,
busy=busy,
frame_error=frame_error)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_eth_hdr_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:])
input_eth_payload_tdata = Signal(intbv(0)[8:])
input_eth_payload_tvalid = Signal(bool(0))
input_eth_payload_tlast = Signal(bool(0))
input_eth_payload_tuser = Signal(bool(0))
output_frame_ready = Signal(bool(0))
# Outputs
input_eth_hdr_ready = Signal(bool(0))
input_eth_payload_tready = Signal(bool(0))
output_frame_valid = Signal(bool(0))
output_eth_dest_mac = Signal(intbv(0)[48:])
output_eth_src_mac = Signal(intbv(0)[48:])
output_eth_type = Signal(intbv(0)[16:])
output_arp_htype = Signal(intbv(0)[16:])
output_arp_ptype = Signal(intbv(0)[16:])
output_arp_hlen = Signal(intbv(0)[8:])
output_arp_plen = Signal(intbv(0)[8:])
output_arp_oper = Signal(intbv(0)[16:])
output_arp_sha = Signal(intbv(0)[48:])
output_arp_spa = Signal(intbv(0)[32:])
output_arp_tha = Signal(intbv(0)[48:])
output_arp_tpa = Signal(intbv(0)[32:])
busy = Signal(bool(0))
frame_error = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = eth_ep.EthFrameSource(clk,
rst,
eth_hdr_ready=input_eth_hdr_ready,
eth_hdr_valid=input_eth_hdr_valid,
eth_dest_mac=input_eth_dest_mac,
eth_src_mac=input_eth_src_mac,
eth_type=input_eth_type,
eth_payload_tdata=input_eth_payload_tdata,
eth_payload_tvalid=input_eth_payload_tvalid,
eth_payload_tready=input_eth_payload_tready,
eth_payload_tlast=input_eth_payload_tlast,
eth_payload_tuser=input_eth_payload_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = arp_ep.ARPFrameSink(clk,
rst,
frame_ready=output_frame_ready,
frame_valid=output_frame_valid,
eth_dest_mac=output_eth_dest_mac,
eth_src_mac=output_eth_src_mac,
eth_type=output_eth_type,
arp_htype=output_arp_htype,
arp_ptype=output_arp_ptype,
arp_hlen=output_arp_hlen,
arp_plen=output_arp_plen,
arp_oper=output_arp_oper,
arp_sha=output_arp_sha,
arp_spa=output_arp_spa,
arp_tha=output_arp_tha,
arp_tpa=output_arp_tpa,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_arp_eth_rx(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_frame_valid,
output_frame_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_arp_htype,
output_arp_ptype,
output_arp_hlen,
output_arp_plen,
output_arp_oper,
output_arp_sha,
output_arp_spa,
output_arp_tha,
output_arp_tpa,
busy,
frame_error)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame.build_eth())
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: packet with trailing bytes")
current_test.next = 2
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
eth_frame = test_frame.build_eth()
eth_frame.payload.data += bytearray(range(10))
source_queue.put(eth_frame)
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame.build_eth())
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1.build_eth())
source_queue.put(test_frame2.build_eth())
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1.build_eth())
source_queue.put(test_frame2.build_eth())
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1.build_eth())
source_queue.put(test_frame2.build_eth())
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: truncated packet")
current_test.next = 7
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
eth_frame = test_frame.build_eth()
eth_frame.payload.data = eth_frame.payload.data[:-2]
source_queue.put(eth_frame)
yield clk.posedge
yield input_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
assert frame_error
yield delay(100)
yield clk.posedge
print("test 7: bad header")
current_test.next = 7
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame.build_eth())
yield clk.posedge
yield input_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
#assert frame_error
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

137
tb/test_arp_eth_rx.v Normal file
View File

@ -0,0 +1,137 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arp_eth_rx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_eth_hdr_valid = 0;
reg [47:0] input_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [7:0] input_eth_payload_tdata = 0;
reg input_eth_payload_tvalid = 0;
reg input_eth_payload_tlast = 0;
reg input_eth_payload_tuser = 0;
reg output_frame_ready = 0;
// Outputs
wire input_eth_hdr_ready;
wire input_eth_payload_tready;
wire output_frame_valid;
wire [47:0] output_eth_dest_mac;
wire [47:0] output_eth_src_mac;
wire [15:0] output_eth_type;
wire [15:0] output_arp_htype;
wire [15:0] output_arp_ptype;
wire [7:0] output_arp_hlen;
wire [7:0] output_arp_plen;
wire [15:0] output_arp_oper;
wire [47:0] output_arp_sha;
wire [31:0] output_arp_spa;
wire [47:0] output_arp_tha;
wire [31:0] output_arp_tpa;
wire busy;
wire frame_error;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tvalid,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_frame_ready);
$to_myhdl(input_eth_hdr_ready,
input_eth_payload_tready,
output_frame_valid,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_arp_htype,
output_arp_ptype,
output_arp_hlen,
output_arp_plen,
output_arp_oper,
output_arp_sha,
output_arp_spa,
output_arp_tha,
output_arp_tpa,
busy,
frame_error);
// dump file
$dumpfile("test_arp_eth_rx.lxt");
$dumpvars(0, test_arp_eth_rx);
end
arp_eth_rx
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.input_eth_hdr_valid(input_eth_hdr_valid),
.input_eth_hdr_ready(input_eth_hdr_ready),
.input_eth_dest_mac(input_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac),
.input_eth_type(input_eth_type),
.input_eth_payload_tdata(input_eth_payload_tdata),
.input_eth_payload_tvalid(input_eth_payload_tvalid),
.input_eth_payload_tready(input_eth_payload_tready),
.input_eth_payload_tlast(input_eth_payload_tlast),
.input_eth_payload_tuser(input_eth_payload_tuser),
// ARP frame output
.output_frame_valid(output_frame_valid),
.output_frame_ready(output_frame_ready),
.output_eth_dest_mac(output_eth_dest_mac),
.output_eth_src_mac(output_eth_src_mac),
.output_eth_type(output_eth_type),
.output_arp_htype(output_arp_htype),
.output_arp_ptype(output_arp_ptype),
.output_arp_hlen(output_arp_hlen),
.output_arp_plen(output_arp_plen),
.output_arp_oper(output_arp_oper),
.output_arp_sha(output_arp_sha),
.output_arp_spa(output_arp_spa),
.output_arp_tha(output_arp_tha),
.output_arp_tpa(output_arp_tpa),
// Status signals
.busy(busy),
.frame_error(frame_error)
);
endmodule

600
tb/test_arp_eth_rx_64.py Executable file
View File

@ -0,0 +1,600 @@
#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import arp_ep
import eth_ep
module = 'arp_eth_rx_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arp_eth_rx_64(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tkeep,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_frame_valid,
output_frame_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_arp_htype,
output_arp_ptype,
output_arp_hlen,
output_arp_plen,
output_arp_oper,
output_arp_sha,
output_arp_spa,
output_arp_tha,
output_arp_tpa,
busy,
frame_error):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_eth_hdr_valid=input_eth_hdr_valid,
input_eth_hdr_ready=input_eth_hdr_ready,
input_eth_dest_mac=input_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac,
input_eth_type=input_eth_type,
input_eth_payload_tdata=input_eth_payload_tdata,
input_eth_payload_tkeep=input_eth_payload_tkeep,
input_eth_payload_tvalid=input_eth_payload_tvalid,
input_eth_payload_tready=input_eth_payload_tready,
input_eth_payload_tlast=input_eth_payload_tlast,
input_eth_payload_tuser=input_eth_payload_tuser,
output_frame_valid=output_frame_valid,
output_frame_ready=output_frame_ready,
output_eth_dest_mac=output_eth_dest_mac,
output_eth_src_mac=output_eth_src_mac,
output_eth_type=output_eth_type,
output_arp_htype=output_arp_htype,
output_arp_ptype=output_arp_ptype,
output_arp_hlen=output_arp_hlen,
output_arp_plen=output_arp_plen,
output_arp_oper=output_arp_oper,
output_arp_sha=output_arp_sha,
output_arp_spa=output_arp_spa,
output_arp_tha=output_arp_tha,
output_arp_tpa=output_arp_tpa,
busy=busy,
frame_error=frame_error)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_eth_hdr_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:])
input_eth_payload_tdata = Signal(intbv(0)[64:])
input_eth_payload_tkeep = Signal(intbv(0)[8:])
input_eth_payload_tvalid = Signal(bool(0))
input_eth_payload_tlast = Signal(bool(0))
input_eth_payload_tuser = Signal(bool(0))
output_frame_ready = Signal(bool(0))
# Outputs
input_eth_hdr_ready = Signal(bool(0))
input_eth_payload_tready = Signal(bool(0))
output_frame_valid = Signal(bool(0))
output_eth_dest_mac = Signal(intbv(0)[48:])
output_eth_src_mac = Signal(intbv(0)[48:])
output_eth_type = Signal(intbv(0)[16:])
output_arp_htype = Signal(intbv(0)[16:])
output_arp_ptype = Signal(intbv(0)[16:])
output_arp_hlen = Signal(intbv(0)[8:])
output_arp_plen = Signal(intbv(0)[8:])
output_arp_oper = Signal(intbv(0)[16:])
output_arp_sha = Signal(intbv(0)[48:])
output_arp_spa = Signal(intbv(0)[32:])
output_arp_tha = Signal(intbv(0)[48:])
output_arp_tpa = Signal(intbv(0)[32:])
busy = Signal(bool(0))
frame_error = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = eth_ep.EthFrameSource(clk,
rst,
eth_hdr_ready=input_eth_hdr_ready,
eth_hdr_valid=input_eth_hdr_valid,
eth_dest_mac=input_eth_dest_mac,
eth_src_mac=input_eth_src_mac,
eth_type=input_eth_type,
eth_payload_tdata=input_eth_payload_tdata,
eth_payload_tkeep=input_eth_payload_tkeep,
eth_payload_tvalid=input_eth_payload_tvalid,
eth_payload_tready=input_eth_payload_tready,
eth_payload_tlast=input_eth_payload_tlast,
eth_payload_tuser=input_eth_payload_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = arp_ep.ARPFrameSink(clk,
rst,
frame_ready=output_frame_ready,
frame_valid=output_frame_valid,
eth_dest_mac=output_eth_dest_mac,
eth_src_mac=output_eth_src_mac,
eth_type=output_eth_type,
arp_htype=output_arp_htype,
arp_ptype=output_arp_ptype,
arp_hlen=output_arp_hlen,
arp_plen=output_arp_plen,
arp_oper=output_arp_oper,
arp_sha=output_arp_sha,
arp_spa=output_arp_spa,
arp_tha=output_arp_tha,
arp_tpa=output_arp_tpa,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_arp_eth_rx_64(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tkeep,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_frame_valid,
output_frame_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_arp_htype,
output_arp_ptype,
output_arp_hlen,
output_arp_plen,
output_arp_oper,
output_arp_sha,
output_arp_spa,
output_arp_tha,
output_arp_tpa,
busy,
frame_error)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame.build_eth())
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: packet with trailing bytes")
current_test.next = 2
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
eth_frame = test_frame.build_eth()
eth_frame.payload.data += bytearray(range(10))
source_queue.put(eth_frame)
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame.build_eth())
yield clk.posedge
yield delay(16)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(16)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
#yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1.build_eth())
source_queue.put(test_frame2.build_eth())
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield output_frame_valid.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1.build_eth())
source_queue.put(test_frame2.build_eth())
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1.build_eth())
source_queue.put(test_frame2.build_eth())
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: truncated packet")
current_test.next = 7
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
eth_frame = test_frame.build_eth()
eth_frame.payload.data = eth_frame.payload.data[:-2]
source_queue.put(eth_frame)
yield clk.posedge
yield input_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
assert frame_error
yield delay(100)
yield clk.posedge
print("test 7: bad header")
current_test.next = 7
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame.build_eth())
yield clk.posedge
yield input_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
#assert frame_error
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

140
tb/test_arp_eth_rx_64.v Normal file
View File

@ -0,0 +1,140 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arp_eth_rx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_eth_hdr_valid = 0;
reg [47:0] input_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [63:0] input_eth_payload_tdata = 0;
reg [7:0] input_eth_payload_tkeep = 0;
reg input_eth_payload_tvalid = 0;
reg input_eth_payload_tlast = 0;
reg input_eth_payload_tuser = 0;
reg output_frame_ready = 0;
// Outputs
wire input_eth_hdr_ready;
wire input_eth_payload_tready;
wire output_frame_valid;
wire [47:0] output_eth_dest_mac;
wire [47:0] output_eth_src_mac;
wire [15:0] output_eth_type;
wire [15:0] output_arp_htype;
wire [15:0] output_arp_ptype;
wire [7:0] output_arp_hlen;
wire [7:0] output_arp_plen;
wire [15:0] output_arp_oper;
wire [47:0] output_arp_sha;
wire [31:0] output_arp_spa;
wire [47:0] output_arp_tha;
wire [31:0] output_arp_tpa;
wire busy;
wire frame_error;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tkeep,
input_eth_payload_tvalid,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_frame_ready);
$to_myhdl(input_eth_hdr_ready,
input_eth_payload_tready,
output_frame_valid,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_arp_htype,
output_arp_ptype,
output_arp_hlen,
output_arp_plen,
output_arp_oper,
output_arp_sha,
output_arp_spa,
output_arp_tha,
output_arp_tpa,
busy,
frame_error);
// dump file
$dumpfile("test_arp_eth_rx_64.lxt");
$dumpvars(0, test_arp_eth_rx_64);
end
arp_eth_rx_64
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.input_eth_hdr_valid(input_eth_hdr_valid),
.input_eth_hdr_ready(input_eth_hdr_ready),
.input_eth_dest_mac(input_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac),
.input_eth_type(input_eth_type),
.input_eth_payload_tdata(input_eth_payload_tdata),
.input_eth_payload_tkeep(input_eth_payload_tkeep),
.input_eth_payload_tvalid(input_eth_payload_tvalid),
.input_eth_payload_tready(input_eth_payload_tready),
.input_eth_payload_tlast(input_eth_payload_tlast),
.input_eth_payload_tuser(input_eth_payload_tuser),
// ARP frame output
.output_frame_valid(output_frame_valid),
.output_frame_ready(output_frame_ready),
.output_eth_dest_mac(output_eth_dest_mac),
.output_eth_src_mac(output_eth_src_mac),
.output_eth_type(output_eth_type),
.output_arp_htype(output_arp_htype),
.output_arp_ptype(output_arp_ptype),
.output_arp_hlen(output_arp_hlen),
.output_arp_plen(output_arp_plen),
.output_arp_oper(output_arp_oper),
.output_arp_sha(output_arp_sha),
.output_arp_spa(output_arp_spa),
.output_arp_tha(output_arp_tha),
.output_arp_tpa(output_arp_tpa),
// Status signals
.busy(busy),
.frame_error(frame_error)
);
endmodule

472
tb/test_arp_eth_tx.py Executable file
View File

@ -0,0 +1,472 @@
#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
import arp_ep
module = 'arp_eth_tx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arp_eth_tx(clk,
rst,
current_test,
input_frame_valid,
input_frame_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
input_arp_tha,
input_arp_tpa,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_frame_valid=input_frame_valid,
input_frame_ready=input_frame_ready,
input_eth_dest_mac=input_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac,
input_eth_type=input_eth_type,
input_arp_htype=input_arp_htype,
input_arp_ptype=input_arp_ptype,
input_arp_hlen=input_arp_hlen,
input_arp_plen=input_arp_plen,
input_arp_oper=input_arp_oper,
input_arp_sha=input_arp_sha,
input_arp_spa=input_arp_spa,
input_arp_tha=input_arp_tha,
input_arp_tpa=input_arp_tpa,
output_eth_hdr_valid=output_eth_hdr_valid,
output_eth_hdr_ready=output_eth_hdr_ready,
output_eth_dest_mac=output_eth_dest_mac,
output_eth_src_mac=output_eth_src_mac,
output_eth_type=output_eth_type,
output_eth_payload_tdata=output_eth_payload_tdata,
output_eth_payload_tvalid=output_eth_payload_tvalid,
output_eth_payload_tready=output_eth_payload_tready,
output_eth_payload_tlast=output_eth_payload_tlast,
output_eth_payload_tuser=output_eth_payload_tuser,
busy=busy)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_frame_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:])
input_arp_htype = Signal(intbv(0)[16:])
input_arp_ptype = Signal(intbv(0)[16:])
input_arp_hlen = Signal(intbv(0)[8:])
input_arp_plen = Signal(intbv(0)[8:])
input_arp_oper = Signal(intbv(0)[16:])
input_arp_sha = Signal(intbv(0)[48:])
input_arp_spa = Signal(intbv(0)[32:])
input_arp_tha = Signal(intbv(0)[48:])
input_arp_tpa = Signal(intbv(0)[32:])
output_eth_payload_tready = Signal(bool(0))
output_eth_hdr_ready = Signal(bool(0))
# Outputs
input_frame_ready = Signal(bool(0))
output_eth_hdr_valid = Signal(bool(0))
output_eth_dest_mac = Signal(intbv(0)[48:])
output_eth_src_mac = Signal(intbv(0)[48:])
output_eth_type = Signal(intbv(0)[16:])
output_eth_payload_tdata = Signal(intbv(0)[8:])
output_eth_payload_tvalid = Signal(bool(0))
output_eth_payload_tlast = Signal(bool(0))
output_eth_payload_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = arp_ep.ARPFrameSource(clk,
rst,
frame_ready=input_frame_ready,
frame_valid=input_frame_valid,
eth_dest_mac=input_eth_dest_mac,
eth_src_mac=input_eth_src_mac,
eth_type=input_eth_type,
arp_htype=input_arp_htype,
arp_ptype=input_arp_ptype,
arp_hlen=input_arp_hlen,
arp_plen=input_arp_plen,
arp_oper=input_arp_oper,
arp_sha=input_arp_sha,
arp_spa=input_arp_spa,
arp_tha=input_arp_tha,
arp_tpa=input_arp_tpa,
fifo=source_queue,
pause=source_pause,
name='source')
sink = eth_ep.EthFrameSink(clk,
rst,
eth_hdr_ready=output_eth_hdr_ready,
eth_hdr_valid=output_eth_hdr_valid,
eth_dest_mac=output_eth_dest_mac,
eth_src_mac=output_eth_src_mac,
eth_type=output_eth_type,
eth_payload_tdata=output_eth_payload_tdata,
eth_payload_tvalid=output_eth_payload_tvalid,
eth_payload_tready=output_eth_payload_tready,
eth_payload_tlast=output_eth_payload_tlast,
eth_payload_tuser=output_eth_payload_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_arp_eth_tx(clk,
rst,
current_test,
input_frame_valid,
input_frame_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
input_arp_tha,
input_arp_tpa,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test packet with pauses")
current_test.next = 2
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets")
current_test.next = 3
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: alternate pause sink")
current_test.next = 4
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while output_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: bad header")
current_test.next = 7
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
#assert frame_error
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

134
tb/test_arp_eth_tx.v Normal file
View File

@ -0,0 +1,134 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arp_eth_tx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_frame_valid = 0;
reg [47:0] input_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [15:0] input_arp_htype = 0;
reg [15:0] input_arp_ptype = 0;
reg [7:0] input_arp_hlen = 0;
reg [7:0] input_arp_plen = 0;
reg [15:0] input_arp_oper = 0;
reg [47:0] input_arp_sha = 0;
reg [31:0] input_arp_spa = 0;
reg [47:0] input_arp_tha = 0;
reg [31:0] input_arp_tpa = 0;
reg output_eth_hdr_ready = 0;
reg output_eth_payload_tready = 0;
// Outputs
wire input_frame_ready;
wire output_eth_hdr_valid;
wire [47:0] output_eth_dest_mac;
wire [47:0] output_eth_src_mac;
wire [15:0] output_eth_type;
wire [7:0] output_eth_payload_tdata;
wire output_eth_payload_tvalid;
wire output_eth_payload_tlast;
wire output_eth_payload_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_frame_valid,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
input_arp_tha,
input_arp_tpa,
output_eth_hdr_ready,
output_eth_payload_tready);
$to_myhdl(input_frame_ready,
output_eth_hdr_valid,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tvalid,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy);
// dump file
$dumpfile("test_arp_eth_tx.lxt");
$dumpvars(0, test_arp_eth_tx);
end
arp_eth_tx
UUT (
.clk(clk),
.rst(rst),
// ARP frame input
.input_frame_valid(input_frame_valid),
.input_frame_ready(input_frame_ready),
.input_eth_dest_mac(input_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac),
.input_eth_type(input_eth_type),
.input_arp_htype(input_arp_htype),
.input_arp_ptype(input_arp_ptype),
.input_arp_hlen(input_arp_hlen),
.input_arp_plen(input_arp_plen),
.input_arp_oper(input_arp_oper),
.input_arp_sha(input_arp_sha),
.input_arp_spa(input_arp_spa),
.input_arp_tha(input_arp_tha),
.input_arp_tpa(input_arp_tpa),
// Ethernet frame output
.output_eth_hdr_valid(output_eth_hdr_valid),
.output_eth_hdr_ready(output_eth_hdr_ready),
.output_eth_dest_mac(output_eth_dest_mac),
.output_eth_src_mac(output_eth_src_mac),
.output_eth_type(output_eth_type),
.output_eth_payload_tdata(output_eth_payload_tdata),
.output_eth_payload_tvalid(output_eth_payload_tvalid),
.output_eth_payload_tready(output_eth_payload_tready),
.output_eth_payload_tlast(output_eth_payload_tlast),
.output_eth_payload_tuser(output_eth_payload_tuser),
// Status signals
.busy(busy)
);
endmodule

477
tb/test_arp_eth_tx_64.py Executable file
View File

@ -0,0 +1,477 @@
#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
import arp_ep
module = 'arp_eth_tx_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arp_eth_tx_64(clk,
rst,
current_test,
input_frame_valid,
input_frame_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
input_arp_tha,
input_arp_tpa,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tkeep,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_frame_valid=input_frame_valid,
input_frame_ready=input_frame_ready,
input_eth_dest_mac=input_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac,
input_eth_type=input_eth_type,
input_arp_htype=input_arp_htype,
input_arp_ptype=input_arp_ptype,
input_arp_hlen=input_arp_hlen,
input_arp_plen=input_arp_plen,
input_arp_oper=input_arp_oper,
input_arp_sha=input_arp_sha,
input_arp_spa=input_arp_spa,
input_arp_tha=input_arp_tha,
input_arp_tpa=input_arp_tpa,
output_eth_hdr_valid=output_eth_hdr_valid,
output_eth_hdr_ready=output_eth_hdr_ready,
output_eth_dest_mac=output_eth_dest_mac,
output_eth_src_mac=output_eth_src_mac,
output_eth_type=output_eth_type,
output_eth_payload_tdata=output_eth_payload_tdata,
output_eth_payload_tkeep=output_eth_payload_tkeep,
output_eth_payload_tvalid=output_eth_payload_tvalid,
output_eth_payload_tready=output_eth_payload_tready,
output_eth_payload_tlast=output_eth_payload_tlast,
output_eth_payload_tuser=output_eth_payload_tuser,
busy=busy)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_frame_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:])
input_arp_htype = Signal(intbv(0)[16:])
input_arp_ptype = Signal(intbv(0)[16:])
input_arp_hlen = Signal(intbv(0)[8:])
input_arp_plen = Signal(intbv(0)[8:])
input_arp_oper = Signal(intbv(0)[16:])
input_arp_sha = Signal(intbv(0)[48:])
input_arp_spa = Signal(intbv(0)[32:])
input_arp_tha = Signal(intbv(0)[48:])
input_arp_tpa = Signal(intbv(0)[32:])
output_eth_payload_tready = Signal(bool(0))
output_eth_hdr_ready = Signal(bool(0))
# Outputs
input_frame_ready = Signal(bool(0))
output_eth_hdr_valid = Signal(bool(0))
output_eth_dest_mac = Signal(intbv(0)[48:])
output_eth_src_mac = Signal(intbv(0)[48:])
output_eth_type = Signal(intbv(0)[16:])
output_eth_payload_tdata = Signal(intbv(0)[64:])
output_eth_payload_tkeep = Signal(intbv(0)[8:])
output_eth_payload_tvalid = Signal(bool(0))
output_eth_payload_tlast = Signal(bool(0))
output_eth_payload_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = arp_ep.ARPFrameSource(clk,
rst,
frame_ready=input_frame_ready,
frame_valid=input_frame_valid,
eth_dest_mac=input_eth_dest_mac,
eth_src_mac=input_eth_src_mac,
eth_type=input_eth_type,
arp_htype=input_arp_htype,
arp_ptype=input_arp_ptype,
arp_hlen=input_arp_hlen,
arp_plen=input_arp_plen,
arp_oper=input_arp_oper,
arp_sha=input_arp_sha,
arp_spa=input_arp_spa,
arp_tha=input_arp_tha,
arp_tpa=input_arp_tpa,
fifo=source_queue,
pause=source_pause,
name='source')
sink = eth_ep.EthFrameSink(clk,
rst,
eth_hdr_ready=output_eth_hdr_ready,
eth_hdr_valid=output_eth_hdr_valid,
eth_dest_mac=output_eth_dest_mac,
eth_src_mac=output_eth_src_mac,
eth_type=output_eth_type,
eth_payload_tdata=output_eth_payload_tdata,
eth_payload_tkeep=output_eth_payload_tkeep,
eth_payload_tvalid=output_eth_payload_tvalid,
eth_payload_tready=output_eth_payload_tready,
eth_payload_tlast=output_eth_payload_tlast,
eth_payload_tuser=output_eth_payload_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_arp_eth_tx_64(clk,
rst,
current_test,
input_frame_valid,
input_frame_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
input_arp_tha,
input_arp_tpa,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tkeep,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test packet with pauses")
current_test.next = 2
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame)
yield clk.posedge
yield delay(16)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets")
current_test.next = 3
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: alternate pause sink")
current_test.next = 4
test_frame1 = arp_ep.ARPFrame()
test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x0806
test_frame1.arp_htype = 0x0001
test_frame1.arp_ptype = 0x0800
test_frame1.arp_hlen = 6
test_frame1.arp_plen = 4
test_frame1.arp_oper = 1
test_frame1.arp_sha = 0x5A5152535455
test_frame1.arp_spa = 0xc0a80164
test_frame1.arp_tha = 0xDAD1D2D3D4D5
test_frame1.arp_tpa = 0xc0a80165
test_frame2 = arp_ep.ARPFrame()
test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x0806
test_frame2.arp_htype = 0x0001
test_frame2.arp_ptype = 0x0800
test_frame2.arp_hlen = 6
test_frame2.arp_plen = 4
test_frame2.arp_oper = 1
test_frame2.arp_sha = 0x5A5152535455
test_frame2.arp_spa = 0xc0a80164
test_frame2.arp_tha = 0xDAD1D2D3D4D5
test_frame2.arp_tpa = 0xc0a80165
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while output_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: bad header")
current_test.next = 7
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
source_queue.put(test_frame)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
#assert frame_error
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

137
tb/test_arp_eth_tx_64.v Normal file
View File

@ -0,0 +1,137 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arp_eth_tx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_frame_valid = 0;
reg [47:0] input_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [15:0] input_arp_htype = 0;
reg [15:0] input_arp_ptype = 0;
reg [7:0] input_arp_hlen = 0;
reg [7:0] input_arp_plen = 0;
reg [15:0] input_arp_oper = 0;
reg [47:0] input_arp_sha = 0;
reg [31:0] input_arp_spa = 0;
reg [47:0] input_arp_tha = 0;
reg [31:0] input_arp_tpa = 0;
reg output_eth_hdr_ready = 0;
reg output_eth_payload_tready = 0;
// Outputs
wire input_frame_ready;
wire output_eth_hdr_valid;
wire [47:0] output_eth_dest_mac;
wire [47:0] output_eth_src_mac;
wire [15:0] output_eth_type;
wire [63:0] output_eth_payload_tdata;
wire [7:0] output_eth_payload_tkeep;
wire output_eth_payload_tvalid;
wire output_eth_payload_tlast;
wire output_eth_payload_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_frame_valid,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_arp_htype,
input_arp_ptype,
input_arp_hlen,
input_arp_plen,
input_arp_oper,
input_arp_sha,
input_arp_spa,
input_arp_tha,
input_arp_tpa,
output_eth_hdr_ready,
output_eth_payload_tready);
$to_myhdl(input_frame_ready,
output_eth_hdr_valid,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tkeep,
output_eth_payload_tvalid,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy);
// dump file
$dumpfile("test_arp_eth_tx_64.lxt");
$dumpvars(0, test_arp_eth_tx_64);
end
arp_eth_tx_64
UUT (
.clk(clk),
.rst(rst),
// ARP frame input
.input_frame_valid(input_frame_valid),
.input_frame_ready(input_frame_ready),
.input_eth_dest_mac(input_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac),
.input_eth_type(input_eth_type),
.input_arp_htype(input_arp_htype),
.input_arp_ptype(input_arp_ptype),
.input_arp_hlen(input_arp_hlen),
.input_arp_plen(input_arp_plen),
.input_arp_oper(input_arp_oper),
.input_arp_sha(input_arp_sha),
.input_arp_spa(input_arp_spa),
.input_arp_tha(input_arp_tha),
.input_arp_tpa(input_arp_tpa),
// Ethernet frame output
.output_eth_hdr_valid(output_eth_hdr_valid),
.output_eth_hdr_ready(output_eth_hdr_ready),
.output_eth_dest_mac(output_eth_dest_mac),
.output_eth_src_mac(output_eth_src_mac),
.output_eth_type(output_eth_type),
.output_eth_payload_tdata(output_eth_payload_tdata),
.output_eth_payload_tkeep(output_eth_payload_tkeep),
.output_eth_payload_tvalid(output_eth_payload_tvalid),
.output_eth_payload_tready(output_eth_payload_tready),
.output_eth_payload_tlast(output_eth_payload_tlast),
.output_eth_payload_tuser(output_eth_payload_tuser),
// Status signals
.busy(busy)
);
endmodule